1 /*
2 * Copyright (c) 2016 Jean-Paul Etienne <fractalclone@gmail.com>
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include <zephyr/irq.h>
8
9 /*
10 * In RISC-V there is no conventional way to handle CPU power save.
11 * Each RISC-V SOC handles it in its own way.
12 * Hence, by default, arch_cpu_idle and arch_cpu_atomic_idle functions just
13 * unlock interrupts and return to the caller, without issuing any CPU power
14 * saving instruction.
15 *
16 * Nonetheless, define the default arch_cpu_idle and arch_cpu_atomic_idle
17 * functions as weak functions, so that they can be replaced at the SOC-level.
18 */
19
arch_cpu_idle(void)20 void __weak arch_cpu_idle(void)
21 {
22 irq_unlock(MSTATUS_IEN);
23 }
24
arch_cpu_atomic_idle(unsigned int key)25 void __weak arch_cpu_atomic_idle(unsigned int key)
26 {
27 irq_unlock(key);
28 }
29
