1 /* 2 * Copyright (c) 2022 Synopsys. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 /** 8 * @file 9 * @brief save and load macro for ARCv2 DSP and AGU regs 10 * 11 */ 12 .macro _save_dsp_regs 13 #ifdef CONFIG_ARC_DSP_SHARING 14 ld_s r13, [r2, ___thread_base_t_user_options_OFFSET] 15 bbit0 r13, K_DSP_IDX, dsp_skip_save 16 lr r13, [_ARC_V2_DSP_CTRL] 17 st_s r13, [sp, ___callee_saved_stack_t_dsp_ctrl_OFFSET] 18 lr r13, [_ARC_V2_ACC0_GLO] 19 st_s r13, [sp, ___callee_saved_stack_t_acc0_glo_OFFSET] 20 lr r13, [_ARC_V2_ACC0_GHI] 21 st_s r13, [sp, ___callee_saved_stack_t_acc0_ghi_OFFSET] 22 #ifdef CONFIG_ARC_DSP_BFLY_SHARING 23 lr r13, [_ARC_V2_DSP_BFLY0] 24 st_s r13, [sp, ___callee_saved_stack_t_dsp_bfly0_OFFSET] 25 lr r13, [_ARC_V2_DSP_FFT_CTRL] 26 st_s r13, [sp, ___callee_saved_stack_t_dsp_fft_ctrl_OFFSET] 27 #endif 28 #endif 29 dsp_skip_save : 30 #ifdef CONFIG_ARC_AGU_SHARING 31 _save_agu_regs 32 #endif 33 .endm 34 35 .macro _save_agu_regs 36 #ifdef CONFIG_ARC_AGU_SHARING 37 ld_s r13, [r2, ___thread_base_t_user_options_OFFSET] 38 btst r13, K_AGU_IDX 39 40 jeq agu_skip_save 41 42 lr r13, [_ARC_V2_AGU_AP0] 43 st r13, [sp, ___callee_saved_stack_t_agu_ap0_OFFSET] 44 lr r13, [_ARC_V2_AGU_AP1] 45 st r13, [sp, ___callee_saved_stack_t_agu_ap1_OFFSET] 46 lr r13, [_ARC_V2_AGU_AP2] 47 st r13, [sp, ___callee_saved_stack_t_agu_ap2_OFFSET] 48 lr r13, [_ARC_V2_AGU_AP3] 49 st r13, [sp, ___callee_saved_stack_t_agu_ap3_OFFSET] 50 lr r13, [_ARC_V2_AGU_OS0] 51 st r13, [sp, ___callee_saved_stack_t_agu_os0_OFFSET] 52 lr r13, [_ARC_V2_AGU_OS1] 53 st r13, [sp, ___callee_saved_stack_t_agu_os1_OFFSET] 54 lr r13, [_ARC_V2_AGU_MOD0] 55 st r13, [sp, ___callee_saved_stack_t_agu_mod0_OFFSET] 56 lr r13, [_ARC_V2_AGU_MOD1] 57 st r13, [sp, ___callee_saved_stack_t_agu_mod1_OFFSET] 58 lr r13, [_ARC_V2_AGU_MOD2] 59 st r13, [sp, ___callee_saved_stack_t_agu_mod2_OFFSET] 60 lr r13, [_ARC_V2_AGU_MOD3] 61 st r13, [sp, ___callee_saved_stack_t_agu_mod3_OFFSET] 62 #ifdef CONFIG_ARC_AGU_MEDIUM 63 lr r13, [_ARC_V2_AGU_AP4] 64 st r13, [sp, ___callee_saved_stack_t_agu_ap4_OFFSET] 65 lr r13, [_ARC_V2_AGU_AP5] 66 st r13, [sp, ___callee_saved_stack_t_agu_ap5_OFFSET] 67 lr r13, [_ARC_V2_AGU_AP6] 68 st r13, [sp, ___callee_saved_stack_t_agu_ap6_OFFSET] 69 lr r13, [_ARC_V2_AGU_AP7] 70 st r13, [sp, ___callee_saved_stack_t_agu_ap7_OFFSET] 71 lr r13, [_ARC_V2_AGU_OS2] 72 st r13, [sp, ___callee_saved_stack_t_agu_os2_OFFSET] 73 lr r13, [_ARC_V2_AGU_OS3] 74 st r13, [sp, ___callee_saved_stack_t_agu_os3_OFFSET] 75 lr r13, [_ARC_V2_AGU_MOD4] 76 st r13, [sp, ___callee_saved_stack_t_agu_mod4_OFFSET] 77 lr r13, [_ARC_V2_AGU_MOD5] 78 st r13, [sp, ___callee_saved_stack_t_agu_mod5_OFFSET] 79 lr r13, [_ARC_V2_AGU_MOD6] 80 st r13, [sp, ___callee_saved_stack_t_agu_mod6_OFFSET] 81 lr r13, [_ARC_V2_AGU_MOD7] 82 st r13, [sp, ___callee_saved_stack_t_agu_mod7_OFFSET] 83 lr r13, [_ARC_V2_AGU_MOD8] 84 st r13, [sp, ___callee_saved_stack_t_agu_mod8_OFFSET] 85 lr r13, [_ARC_V2_AGU_MOD9] 86 st r13, [sp, ___callee_saved_stack_t_agu_mod9_OFFSET] 87 lr r13, [_ARC_V2_AGU_MOD10] 88 st r13, [sp, ___callee_saved_stack_t_agu_mod10_OFFSET] 89 lr r13, [_ARC_V2_AGU_MOD11] 90 st r13, [sp, ___callee_saved_stack_t_agu_mod11_OFFSET] 91 #endif 92 #ifdef CONFIG_ARC_AGU_LARGE 93 lr r13, [_ARC_V2_AGU_AP8] 94 st r13, [sp, ___callee_saved_stack_t_agu_ap8_OFFSET] 95 lr r13, [_ARC_V2_AGU_AP9] 96 st r13, [sp, ___callee_saved_stack_t_agu_ap9_OFFSET] 97 lr r13, [_ARC_V2_AGU_AP10] 98 st r13, [sp, ___callee_saved_stack_t_agu_ap10_OFFSET] 99 lr r13, [_ARC_V2_AGU_AP11] 100 st r13, [sp, ___callee_saved_stack_t_agu_ap11_OFFSET] 101 lr r13, [_ARC_V2_AGU_OS4] 102 st r13, [sp, ___callee_saved_stack_t_agu_os4_OFFSET] 103 lr r13, [_ARC_V2_AGU_OS5] 104 st r13, [sp, ___callee_saved_stack_t_agu_os5_OFFSET] 105 lr r13, [_ARC_V2_AGU_OS6] 106 st r13, [sp, ___callee_saved_stack_t_agu_os6_OFFSET] 107 lr r13, [_ARC_V2_AGU_OS7] 108 st r13, [sp, ___callee_saved_stack_t_agu_os7_OFFSET] 109 lr r13, [_ARC_V2_AGU_MOD12] 110 st r13, [sp, ___callee_saved_stack_t_agu_mod12_OFFSET] 111 lr r13, [_ARC_V2_AGU_MOD13] 112 st r13, [sp, ___callee_saved_stack_t_agu_mod13_OFFSET] 113 lr r13, [_ARC_V2_AGU_MOD14] 114 st r13, [sp, ___callee_saved_stack_t_agu_mod14_OFFSET] 115 lr r13, [_ARC_V2_AGU_MOD15] 116 st r13, [sp, ___callee_saved_stack_t_agu_mod15_OFFSET] 117 lr r13, [_ARC_V2_AGU_MOD16] 118 st r13, [sp, ___callee_saved_stack_t_agu_mod16_OFFSET] 119 lr r13, [_ARC_V2_AGU_MOD17] 120 st r13, [sp, ___callee_saved_stack_t_agu_mod17_OFFSET] 121 lr r13, [_ARC_V2_AGU_MOD18] 122 st r13, [sp, ___callee_saved_stack_t_agu_mod18_OFFSET] 123 lr r13, [_ARC_V2_AGU_MOD19] 124 st r13, [sp, ___callee_saved_stack_t_agu_mod19_OFFSET] 125 lr r13, [_ARC_V2_AGU_MOD20] 126 st r13, [sp, ___callee_saved_stack_t_agu_mod20_OFFSET] 127 lr r13, [_ARC_V2_AGU_MOD21] 128 _st32_huge_offset r13, sp, ___callee_saved_stack_t_agu_mod21_OFFSET, r1 129 lr r13, [_ARC_V2_AGU_MOD22] 130 _st32_huge_offset r13, sp, ___callee_saved_stack_t_agu_mod22_OFFSET, r1 131 lr r13, [_ARC_V2_AGU_MOD23] 132 _st32_huge_offset r13, sp, ___callee_saved_stack_t_agu_mod23_OFFSET, r1 133 #endif 134 #endif 135 agu_skip_save : 136 .endm 137 138 .macro _load_dsp_regs 139 #ifdef CONFIG_ARC_DSP_SHARING 140 ld_s r13, [r2, ___thread_base_t_user_options_OFFSET] 141 bbit0 r13, K_DSP_IDX, dsp_skip_load 142 ld_s r13, [sp, ___callee_saved_stack_t_dsp_ctrl_OFFSET] 143 sr r13, [_ARC_V2_DSP_CTRL] 144 ld_s r13, [sp, ___callee_saved_stack_t_acc0_glo_OFFSET] 145 sr r13, [_ARC_V2_ACC0_GLO] 146 ld_s r13, [sp, ___callee_saved_stack_t_acc0_ghi_OFFSET] 147 sr r13, [_ARC_V2_ACC0_GHI] 148 #ifdef CONFIG_ARC_DSP_BFLY_SHARING 149 ld_s r13, [sp, ___callee_saved_stack_t_dsp_bfly0_OFFSET] 150 sr r13, [_ARC_V2_DSP_BFLY0] 151 ld_s r13, [sp, ___callee_saved_stack_t_dsp_fft_ctrl_OFFSET] 152 sr r13, [_ARC_V2_DSP_FFT_CTRL] 153 #endif 154 #endif 155 dsp_skip_load : 156 #ifdef CONFIG_ARC_AGU_SHARING 157 _load_agu_regs 158 #endif 159 .endm 160 161 .macro _load_agu_regs 162 #ifdef CONFIG_ARC_AGU_SHARING 163 ld_s r13, [r2, ___thread_base_t_user_options_OFFSET] 164 btst r13, K_AGU_IDX 165 166 jeq agu_skip_load 167 168 ld r13, [sp, ___callee_saved_stack_t_agu_ap0_OFFSET] 169 sr r13, [_ARC_V2_AGU_AP0] 170 ld r13, [sp, ___callee_saved_stack_t_agu_ap1_OFFSET] 171 sr r13, [_ARC_V2_AGU_AP1] 172 ld r13, [sp, ___callee_saved_stack_t_agu_ap2_OFFSET] 173 sr r13, [_ARC_V2_AGU_AP2] 174 ld r13, [sp, ___callee_saved_stack_t_agu_ap3_OFFSET] 175 sr r13, [_ARC_V2_AGU_AP3] 176 ld r13, [sp, ___callee_saved_stack_t_agu_os0_OFFSET] 177 sr r13, [_ARC_V2_AGU_OS0] 178 ld r13, [sp, ___callee_saved_stack_t_agu_os1_OFFSET] 179 sr r13, [_ARC_V2_AGU_OS1] 180 ld r13, [sp, ___callee_saved_stack_t_agu_mod0_OFFSET] 181 sr r13, [_ARC_V2_AGU_MOD0] 182 ld r13, [sp, ___callee_saved_stack_t_agu_mod1_OFFSET] 183 sr r13, [_ARC_V2_AGU_MOD1] 184 ld r13, [sp, ___callee_saved_stack_t_agu_mod2_OFFSET] 185 sr r13, [_ARC_V2_AGU_MOD2] 186 ld r13, [sp, ___callee_saved_stack_t_agu_mod3_OFFSET] 187 sr r13, [_ARC_V2_AGU_MOD3] 188 #ifdef CONFIG_ARC_AGU_MEDIUM 189 ld r13, [sp, ___callee_saved_stack_t_agu_ap4_OFFSET] 190 sr r13, [_ARC_V2_AGU_AP4] 191 ld r13, [sp, ___callee_saved_stack_t_agu_ap5_OFFSET] 192 sr r13, [_ARC_V2_AGU_AP5] 193 ld r13, [sp, ___callee_saved_stack_t_agu_ap6_OFFSET] 194 sr r13, [_ARC_V2_AGU_AP6] 195 ld r13, [sp, ___callee_saved_stack_t_agu_ap7_OFFSET] 196 sr r13, [_ARC_V2_AGU_AP7] 197 ld r13, [sp, ___callee_saved_stack_t_agu_os2_OFFSET] 198 sr r13, [_ARC_V2_AGU_OS2] 199 ld r13, [sp, ___callee_saved_stack_t_agu_os3_OFFSET] 200 sr r13, [_ARC_V2_AGU_OS3] 201 ld r13, [sp, ___callee_saved_stack_t_agu_mod4_OFFSET] 202 sr r13, [_ARC_V2_AGU_MOD4] 203 ld r13, [sp, ___callee_saved_stack_t_agu_mod5_OFFSET] 204 sr r13, [_ARC_V2_AGU_MOD5] 205 ld r13, [sp, ___callee_saved_stack_t_agu_mod6_OFFSET] 206 sr r13, [_ARC_V2_AGU_MOD6] 207 ld r13, [sp, ___callee_saved_stack_t_agu_mod7_OFFSET] 208 sr r13, [_ARC_V2_AGU_MOD7] 209 ld r13, [sp, ___callee_saved_stack_t_agu_mod8_OFFSET] 210 sr r13, [_ARC_V2_AGU_MOD8] 211 ld r13, [sp, ___callee_saved_stack_t_agu_mod9_OFFSET] 212 sr r13, [_ARC_V2_AGU_MOD9] 213 ld r13, [sp, ___callee_saved_stack_t_agu_mod10_OFFSET] 214 sr r13, [_ARC_V2_AGU_MOD10] 215 ld r13, [sp, ___callee_saved_stack_t_agu_mod11_OFFSET] 216 sr r13, [_ARC_V2_AGU_MOD11] 217 #endif 218 #ifdef CONFIG_ARC_AGU_LARGE 219 ld r13, [sp, ___callee_saved_stack_t_agu_ap8_OFFSET] 220 sr r13, [_ARC_V2_AGU_AP8] 221 ld r13, [sp, ___callee_saved_stack_t_agu_ap9_OFFSET] 222 sr r13, [_ARC_V2_AGU_AP9] 223 ld r13, [sp, ___callee_saved_stack_t_agu_ap10_OFFSET] 224 sr r13, [_ARC_V2_AGU_AP10] 225 ld r13, [sp, ___callee_saved_stack_t_agu_ap11_OFFSET] 226 sr r13, [_ARC_V2_AGU_AP11] 227 ld r13, [sp, ___callee_saved_stack_t_agu_os4_OFFSET] 228 sr r13, [_ARC_V2_AGU_OS4] 229 ld r13, [sp, ___callee_saved_stack_t_agu_os5_OFFSET] 230 sr r13, [_ARC_V2_AGU_OS5] 231 ld r13, [sp, ___callee_saved_stack_t_agu_os6_OFFSET] 232 sr r13, [_ARC_V2_AGU_OS6] 233 ld r13, [sp, ___callee_saved_stack_t_agu_os7_OFFSET] 234 sr r13, [_ARC_V2_AGU_OS7] 235 ld r13, [sp, ___callee_saved_stack_t_agu_mod12_OFFSET] 236 sr r13, [_ARC_V2_AGU_MOD12] 237 ld r13, [sp, ___callee_saved_stack_t_agu_mod13_OFFSET] 238 sr r13, [_ARC_V2_AGU_MOD13] 239 ld r13, [sp, ___callee_saved_stack_t_agu_mod14_OFFSET] 240 sr r13, [_ARC_V2_AGU_MOD14] 241 ld r13, [sp, ___callee_saved_stack_t_agu_mod15_OFFSET] 242 sr r13, [_ARC_V2_AGU_MOD15] 243 ld r13, [sp, ___callee_saved_stack_t_agu_mod16_OFFSET] 244 sr r13, [_ARC_V2_AGU_MOD16] 245 ld r13, [sp, ___callee_saved_stack_t_agu_mod17_OFFSET] 246 sr r13, [_ARC_V2_AGU_MOD17] 247 ld r13, [sp, ___callee_saved_stack_t_agu_mod18_OFFSET] 248 sr r13, [_ARC_V2_AGU_MOD18] 249 ld r13, [sp, ___callee_saved_stack_t_agu_mod19_OFFSET] 250 sr r13, [_ARC_V2_AGU_MOD19] 251 ld r13, [sp, ___callee_saved_stack_t_agu_mod20_OFFSET] 252 sr r13, [_ARC_V2_AGU_MOD20] 253 ld r13, [sp, ___callee_saved_stack_t_agu_mod21_OFFSET] 254 sr r13, [_ARC_V2_AGU_MOD21] 255 ld r13, [sp, ___callee_saved_stack_t_agu_mod22_OFFSET] 256 sr r13, [_ARC_V2_AGU_MOD22] 257 ld r13, [sp, ___callee_saved_stack_t_agu_mod23_OFFSET] 258 sr r13, [_ARC_V2_AGU_MOD23] 259 #endif 260 #endif 261 agu_skip_load : 262 .endm 263 264 .macro _dsp_extension_probe 265 #ifdef CONFIG_ARC_DSP_TURNED_OFF 266 mov r0, 0 /* DSP_CTRL_DISABLED_ALL */ 267 sr r0, [_ARC_V2_DSP_CTRL] 268 #endif 269 .endm 270
