1 /* 2 * Copyright (c) 2018 Intel Corporation 3 * SPDX-License-Identifier: Apache-2.0 4 */ 5 6 #ifndef __INTEL_S1000_IOMUX_H 7 #define __INTEL_S1000_IOMUX_H 8 9 /* 10 * +----------------------+-------------------------------------------------+ 11 * | Table of Possible I/O MUX settings | 12 * +----------------------+-------------------------------------------------+ 13 * | Pin group | FUNC_A (Default) | FUNC_B (Available Alternate) | 14 * +----------------------+-------------------------------------------------+ 15 * | PIN_GROUP(EM_DQ) | EM_DQ | MST_DQ | 16 * | PIN_GROUP(GPIO_PWM0) | GPIO | PWM | 17 * | PIN_GROUP(GPIO_PWM1) | GPIO | PWM | 18 * | PIN_GROUP(GPIO_PWM2) | GPIO | PWM | 19 * | PIN_GROUP(GPIO_PWM3) | GPIO | PWM | 20 * | PIN_GROUP(GPIO_PWM4) | GPIO | PWM | 21 * | PIN_GROUP(GPIO_PWM5) | GPIO | PWM | 22 * | PIN_GROUP(GPIO_PWM6) | GPIO | PWM | 23 * | PIN_GROUP(GPIO_PWM7) | GPIO | PWM | 24 * | PIN_GROUP(HOST_IRQ) | HOST_IRQ | GPIO14 | 25 * | PIN_GROUP(HOST_WAKE) | HOST_WAKE | GPIO13 | 26 * | PIN_GROUP(I2S0) | I2S | PDM | 27 * | PIN_GROUP(I2S2) | I2S | GPIO | 28 * | PIN_GROUP(I2S3) | I2S | GPIO | 29 * | PIN_GROUP(MST_SS1) | MST_SS1 | GPIO25 | 30 * | PIN_GROUP(PDM_0_1) | PDM_0_1 | GPIO | 31 * | PIN_GROUP(UART) | UART | GPIO | 32 * | PIN_GROUP(I2C) | I2C0 | I2C1 | 33 * +----------------------+-------------------------------------------------+ 34 */ 35 36 #define PIN_GROUP(group) IOMUX_PINGROUP_ ## group 37 38 /* 39 * IO Selector is a bit encoding of the mux control register and the 40 * bits selecting the mux in the mux control register 41 */ 42 #define IO_SEL(iomux, lsb, msb) ((iomux) | ((lsb) << 8) | ((msb) << 16)) 43 #define IOMUX_INDEX(pingroup) ((pingroup) & BIT_MASK(8)) 44 #define IOMUX_LSB(pingroup) (((pingroup) >> 8) & BIT_MASK(8)) 45 #define IOMUX_MSB(pingroup) (((pingroup) >> 16) & BIT_MASK(8)) 46 47 /* PSRAM DQ/WAIT or SPI Master DQ/DQS */ 48 #define IOMUX_PINGROUP_EM_DQ IO_SEL(0, 25, 25) 49 50 /* GPIO or PWM */ 51 #define IOMUX_PINGROUP_GPIO_PWM0 IO_SEL(1, 0, 1) 52 #define IOMUX_PINGROUP_GPIO_PWM1 IO_SEL(1, 2, 3) 53 #define IOMUX_PINGROUP_GPIO_PWM2 IO_SEL(1, 4, 5) 54 #define IOMUX_PINGROUP_GPIO_PWM3 IO_SEL(1, 6, 7) 55 #define IOMUX_PINGROUP_GPIO_PWM4 IO_SEL(1, 8, 9) 56 #define IOMUX_PINGROUP_GPIO_PWM5 IO_SEL(1, 10, 11) 57 #define IOMUX_PINGROUP_GPIO_PWM6 IO_SEL(1, 12, 13) 58 #define IOMUX_PINGROUP_GPIO_PWM7 IO_SEL(1, 14, 15) 59 60 61 /* HOST_IRQ or GPIO14 */ 62 #define IOMUX_PINGROUP_HOST_IRQ IO_SEL(0, 1, 1) 63 64 /* HOST_WAKE or GPIO13 */ 65 #define IOMUX_PINGROUP_HOST_WAKE IO_SEL(0, 0, 0) 66 67 /* I2S0 or PDM2/3 */ 68 #define IOMUX_PINGROUP_I2S0 IO_SEL(0, 8, 8) 69 70 /* I2S2 or GPIO */ 71 #define IOMUX_PINGROUP_I2S2 IO_SEL(0, 9, 9) 72 /* I2S3 or GPIO */ 73 #define IOMUX_PINGROUP_I2S3 IO_SEL(0, 10, 10) 74 75 /* SPI Master SS #1 MST_SS1 or GPIO 25 */ 76 #define IOMUX_PINGROUP_MST_SS1 IO_SEL(0, 26, 26) 77 78 /* PDM0/1 or GPIO */ 79 #define IOMUX_PINGROUP_PDM_0_1 IO_SEL(0, 11, 11) 80 81 /* UART CTS/RTS or GPIO */ 82 #define IOMUX_PINGROUP_UART IO_SEL(0, 16, 16) 83 84 /* I2C0 or I2C1 */ 85 #define IOMUX_PINGROUP_I2C IO_SEL(2, 0, 0) 86 87 #endif /* __INTEL_S1000_IOMUX_H */ 88
