1 /* 2 * Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef __SOC_H__ 8 #define __SOC_H__ 9 #include <soc/syscon_reg.h> 10 #include <soc/system_reg.h> 11 #include <soc/dport_access.h> 12 #include <soc/soc_caps.h> 13 #include <esp32s2/rom/ets_sys.h> 14 #include <esp32s2/rom/spi_flash.h> 15 #include <esp32s2/rom/cache.h> 16 17 #include <zephyr/types.h> 18 #include <stdbool.h> 19 #include <arch/xtensa/arch.h> 20 21 extern void esp_rom_uart_attach(void); 22 extern void esp_rom_uart_tx_wait_idle(uint8_t uart_no); 23 extern STATUS esp_rom_uart_tx_one_char(uint8_t chr); 24 extern STATUS esp_rom_uart_rx_one_char(uint8_t *chr); 25 26 /* cache related rom functions */ 27 extern uint32_t esp_rom_Cache_Disable_ICache(void); 28 extern uint32_t esp_rom_Cache_Disable_DCache(void); 29 30 extern void esp_rom_Cache_Allocate_SRAM(cache_layout_t sram0_layout, cache_layout_t sram1_layout, 31 cache_layout_t sram2_layout, cache_layout_t sram3_layout); 32 33 extern uint32_t esp_rom_Cache_Suspend_ICache(void); 34 35 extern void esp_rom_Cache_Set_ICache_Mode(cache_size_t cache_size, cache_ways_t ways, 36 cache_line_size_t cache_line_size); 37 38 extern void esp_rom_Cache_Invalidate_ICache_All(void); 39 void esp_rom_Cache_Resume_ICache(uint32_t autoload); 40 41 #endif /* __SOC_H__ */ 42
