1 /*
2 * Copyright (c) 2017 Intel Corporation
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #ifndef __SOC_H__
8 #define __SOC_H__
9 #include <soc/dport_reg.h>
10 #include <soc/rtc_cntl_reg.h>
11 #include <soc/soc_caps.h>
12 #include <esp32/rom/ets_sys.h>
13 #include <esp32/rom/spi_flash.h>
14
15 #include <zephyr/types.h>
16 #include <stdbool.h>
17 #include <arch/xtensa/arch.h>
18
esp32_set_mask32(uint32_t v,uint32_t mem_addr)19 static inline void esp32_set_mask32(uint32_t v, uint32_t mem_addr)
20 {
21 sys_write32(sys_read32(mem_addr) | v, mem_addr);
22 }
23
esp32_clear_mask32(uint32_t v,uint32_t mem_addr)24 static inline void esp32_clear_mask32(uint32_t v, uint32_t mem_addr)
25 {
26 sys_write32(sys_read32(mem_addr) & ~v, mem_addr);
27 }
28
29 extern void esp32_rom_intr_matrix_set(int cpu_no, uint32_t model_num, uint32_t intr_num);
30
31 extern int esp32_rom_gpio_matrix_in(uint32_t gpio, uint32_t signal_index,
32 bool inverted);
33 extern int esp32_rom_gpio_matrix_out(uint32_t gpio, uint32_t signal_index,
34 bool out_inverted,
35 bool out_enabled_inverted);
36
37 extern void esp32_rom_uart_attach(void);
38 extern void esp32_rom_uart_tx_wait_idle(uint8_t uart_no);
39 extern STATUS esp32_rom_uart_tx_one_char(uint8_t chr);
40 extern STATUS esp32_rom_uart_rx_one_char(uint8_t *chr);
41
42 extern void esp32_rom_Cache_Flush(int cpu);
43 extern void esp32_rom_Cache_Read_Enable(int cpu);
44 extern void esp32_rom_ets_set_appcpu_boot_addr(void *addr);
45
46 /* ROM functions which read/write internal i2c control bus for PLL, APLL */
47 extern uint8_t esp32_rom_i2c_readReg(uint8_t block, uint8_t host_id, uint8_t reg_add);
48 extern void esp32_rom_i2c_writeReg(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data);
49
50 /* ROM information related to SPI Flash chip timing and device */
51 extern esp_rom_spiflash_chip_t g_rom_flashchip;
52 extern uint8_t g_rom_spiflash_dummy_len_plus[];
53
54 #endif /* __SOC_H__ */
55
