1 /* 2 * Copyright (c) 2020 Linaro Limited 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 /** 8 * @file 9 * @brief System/hardware module for STM32L5 processor 10 */ 11 12 #include <device.h> 13 #include <init.h> 14 #include <stm32_ll_bus.h> 15 #include <stm32_ll_pwr.h> 16 #include <arch/cpu.h> 17 #include <arch/arm/aarch32/cortex_m/cmsis.h> 18 #include <stm32l5xx_ll_icache.h> 19 #include <logging/log.h> 20 21 #define LOG_LEVEL CONFIG_SOC_LOG_LEVEL 22 LOG_MODULE_REGISTER(soc); 23 24 /** 25 * @brief Perform basic hardware initialization at boot. 26 * 27 * This needs to be run from the very beginning. 28 * So the init priority has to be 0 (zero). 29 * 30 * @return 0 31 */ stm32l5_init(const struct device * arg)32static int stm32l5_init(const struct device *arg) 33 { 34 uint32_t key; 35 36 ARG_UNUSED(arg); 37 38 /* Enable ICACHE */ 39 while (LL_ICACHE_IsActiveFlag_BUSY()) { 40 } 41 LL_ICACHE_Enable(); 42 43 key = irq_lock(); 44 45 /* Install default handler that simply resets the CPU 46 * if configured in the kernel, NOP otherwise 47 */ 48 NMI_INIT(); 49 50 irq_unlock(key); 51 52 /* Update CMSIS SystemCoreClock variable (HCLK) */ 53 /* At reset, system core clock is set to 4 MHz from MSI */ 54 SystemCoreClock = 4000000; 55 56 /* Enable Scale 0 to achieve 110MHz */ 57 LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR); 58 LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE0); 59 60 /* Disable USB Type-C dead battery pull-down behavior */ 61 LL_PWR_DisableUCPDDeadBattery(); 62 63 return 0; 64 } 65 66 SYS_INIT(stm32l5_init, PRE_KERNEL_1, 0); 67
