1 /* 2 * Copyright (c) 2019 Linaro Limited 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 /** 8 * @file 9 * @brief System/hardware module for STM32H7 CM4 processor 10 */ 11 12 #include <kernel.h> 13 #include <device.h> 14 #include <init.h> 15 #include <soc.h> 16 #include <stm32_ll_bus.h> 17 #include <stm32_ll_cortex.h> 18 #include <stm32_ll_pwr.h> 19 #include <stm32_ll_rcc.h> 20 #include <stm32_ll_system.h> 21 #include <arch/cpu.h> 22 #include <arch/arm/aarch32/cortex_m/cmsis.h> 23 #include "stm32_hsem.h" 24 25 /** 26 * @brief Perform basic hardware initialization at boot. 27 * 28 * This needs to be run from the very beginning. 29 * So the init priority has to be 0 (zero). 30 * 31 * @return 0 32 */ stm32h7_m4_init(const struct device * arg)33static int stm32h7_m4_init(const struct device *arg) 34 { 35 uint32_t key; 36 37 /* Enable ART Flash cache accelerator */ 38 LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_ART); 39 LL_ART_SetBaseAddress(DT_REG_ADDR(DT_CHOSEN(zephyr_flash))); 40 LL_ART_Enable(); 41 42 key = irq_lock(); 43 44 /* Install default handler that simply resets the CPU 45 * if configured in the kernel, NOP otherwise 46 */ 47 NMI_INIT(); 48 49 irq_unlock(key); 50 51 /* In case CM4 has not been forced boot by CM7, 52 * CM4 needs to wait until CM7 has setup clock configuration 53 */ 54 if (!LL_RCC_IsCM4BootForced()) { 55 /* 56 * Domain D2 is waiting for Cortex-M7 to perform 57 * system initialization 58 * (system clock config, external memory configuration.. ). 59 * End of system initialization is reached when CM7 takes HSEM. 60 */ 61 LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_HSEM); 62 while ((HSEM->RLR[CFG_HW_ENTRY_STOP_MODE_SEMID] & HSEM_R_LOCK) 63 != HSEM_R_LOCK) 64 ; 65 } 66 67 return 0; 68 } 69 70 SYS_INIT(stm32h7_m4_init, PRE_KERNEL_1, 0); 71
