1 /* 2 * Copyright (c) 2016 Open-RnD Sp. z o.o. 3 * Copyright (c) 2016 Linaro Limited. 4 * 5 * SPDX-License-Identifier: Apache-2.0 6 */ 7 8 /** 9 * @file 10 * @brief System/hardware module for STM32F4 processor 11 */ 12 13 #include <device.h> 14 #include <init.h> 15 #include <arch/cpu.h> 16 #include <arch/arm/aarch32/cortex_m/cmsis.h> 17 #include <stm32_ll_system.h> 18 19 /** 20 * @brief Perform basic hardware initialization at boot. 21 * 22 * This needs to be run from the very beginning. 23 * So the init priority has to be 0 (zero). 24 * 25 * @return 0 26 */ st_stm32f4_init(const struct device * arg)27static int st_stm32f4_init(const struct device *arg) 28 { 29 uint32_t key; 30 31 ARG_UNUSED(arg); 32 33 /* Enable ART Flash cache accelerator for both instruction and data */ 34 LL_FLASH_EnableInstCache(); 35 LL_FLASH_EnableDataCache(); 36 37 key = irq_lock(); 38 39 /* Install default handler that simply resets the CPU 40 * if configured in the kernel, NOP otherwise 41 */ 42 NMI_INIT(); 43 44 irq_unlock(key); 45 46 /* Update CMSIS SystemCoreClock variable (HCLK) */ 47 /* At reset, system core clock is set to 16 MHz from HSI */ 48 SystemCoreClock = 16000000; 49 50 return 0; 51 } 52 53 SYS_INIT(st_stm32f4_init, PRE_KERNEL_1, 0); 54
