1 /* 2 * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef _MEC_WDT_H 8 #define _MEC_WDT_H 9 10 #include <stdint.h> 11 #include <stddef.h> 12 13 /* Load register */ 14 #define MCHP_WDT_LOAD_REG_OFS 0x00u 15 #define MCHP_WDT_LOAD_REG_MASK 0xffffu 16 17 /* Control register */ 18 #define MCHP_WDT_CTRL_REG_OFS 0x04u 19 #define MCHP_WDT_CTRL_REG_MASK 0x021du 20 #define MCHP_WDT_CTRL_EN_POS 0u 21 #define MCHP_WDT_CTRL_EN_MASK BIT(MCHP_WDT_CTRL_EN_POS) 22 #define MCHP_WDT_CTRL_EN BIT(MCHP_WDT_CTRL_EN_POS) 23 #define MCHP_WDT_CTRL_HTMR_STALL_POS 2u 24 #define MCHP_WDT_CTRL_HTMR_STALL_MASK BIT(MCHP_WDT_CTRL_HTMR_STALL_POS) 25 #define MCHP_WDT_CTRL_HTMR_STALL_EN BIT(MCHP_WDT_CTRL_HTMR_STALL_POS) 26 #define MCHP_WDT_CTRL_WKTMR_STALL_POS 3u 27 #define MCHP_WDT_CTRL_WKTMR_STALL_MASK BIT(MCHP_WDT_CTRL_WKTMR_STALL_POS) 28 #define MCHP_WDT_CTRL_WKTMR_STALL_EN BIT(MCHP_WDT_CTRL_WKTMR_STALL_POS) 29 #define MCHP_WDT_CTRL_JTAG_STALL_POS 4u 30 #define MCHP_WDT_CTRL_JTAG_STALL_MASK BIT(MCHP_WDT_CTRL_JTAG_STALL_POS) 31 #define MCHP_WDT_CTRL_JTAG_STALL_EN BIT(MCHP_WDT_CTRL_JTAG_STALL_POS) 32 /* 33 * WDT mode selecting action taken upon count expiration. 34 * 0 = Generate chip reset 35 * 1 = Clear this bit, 36 * Set event status 37 * Generate interrupt if event IEN bit is set 38 * Kick WDT causing it to reload from LOAD register 39 * If interrupt is enabled in GIRQ21 and NVIC then the EC will jump 40 * to the WDT ISR. 41 */ 42 #define MCHP_WDT_CTRL_MODE_POS 9u 43 #define MCHP_WDT_CTRL_MODE_MASK BIT(MCHP_WDT_CTRL_MODE_POS) 44 #define MCHP_WDT_CTRL_MODE_RESET 0u 45 #define MCHP_WDT_CTRL_MODE_IRQ BIT(MCHP_WDT_CTRL_MODE_POS) 46 47 /* WDT Kick register. Write any value to reload counter */ 48 #define MCHP_WDT_KICK_REG_OFS 0x08u 49 #define MCHP_WDT_KICK_REG_MASK 0xffu 50 #define MCHP_WDT_KICK_VAL 0 51 52 /* WDT Count register. Read only */ 53 #define MCHP_WDT_CNT_RO_REG_OFS 0x0cu 54 #define MCHP_WDT_CNT_RO_REG_MASK 0xffffu 55 56 /* Status Register */ 57 #define MCHP_WDT_STS_REG_OFS 0x10u 58 #define MCHP_WDT_STS_REG_MASK 0x01u 59 #define MCHP_WDT_STS_EVENT_IRQ_POS 0u 60 #define MCHP_WDT_STS_EVENT_IRQ BIT(MCHP_WDT_STS_EVENT_IRQ_POS) 61 62 /* Interrupt Enable Register */ 63 #define MCHP_WDT_IEN_REG_OFS 0x14u 64 #define MCHP_WDT_IEN_REG_MASK 0x01u 65 #define MCHP_WDT_IEN_EVENT_IRQ_POS 0u 66 #define MCHP_WDT_IEN_EVENT_IRQ_MASK BIT(MCHP_WDT_IEN_EVENT_IRQ_POS) 67 #define MCHP_WDT_IEN_EVENT_IRQ_EN BIT(MCHP_WDT_IEN_EVENT_IRQ_POS) 68 69 /** @brief Watchdog timer. Size = 24(0x18) */ 70 struct wdt_regs { 71 volatile uint16_t LOAD; 72 uint8_t RSVD1[2]; 73 volatile uint16_t CTRL; 74 uint8_t RSVD2[2]; 75 volatile uint8_t KICK; 76 uint8_t RSVD3[3]; 77 volatile uint16_t CNT; 78 uint8_t RSVD4[2]; 79 volatile uint16_t STS; 80 uint8_t RSVD5[2]; 81 volatile uint8_t IEN; 82 }; 83 84 #endif /* #ifndef _MEC_WDT_H */ 85
