1 /*
2  * Copyright (c) 2016 Cadence Design Systems, Inc.
3  * Copyright (c) 2019 Stephanos Ioannidis <root@stephanos.io>
4  *
5  * SPDX-License-Identifier: Apache-2.0
6  */
7 
8 #ifndef ZEPHYR_INCLUDE_ARCH_XTENSA_ARCH_INLINES_H_
9 #define ZEPHYR_INCLUDE_ARCH_XTENSA_ARCH_INLINES_H_
10 
11 #ifndef _ASMLANGUAGE
12 
13 #include <kernel_structs.h>
14 
15 #define RSR(sr) \
16 	({uint32_t v; \
17 	 __asm__ volatile ("rsr." sr " %0" : "=a"(v)); \
18 	 v; })
19 
20 #define WSR(sr, v) \
21 	do { \
22 		__asm__ volatile ("wsr." sr " %0" : : "r"(v)); \
23 	} while (false)
24 
arch_curr_cpu(void)25 static ALWAYS_INLINE _cpu_t *arch_curr_cpu(void)
26 {
27 	_cpu_t *cpu;
28 
29 	cpu = (_cpu_t *)RSR(CONFIG_XTENSA_KERNEL_CPU_PTR_SR);
30 
31 	return cpu;
32 }
33 
34 #endif /* !_ASMLANGUAGE */
35 
36 #endif /* ZEPHYR_INCLUDE_ARCH_XTENSA_ARCH_INLINES_H_ */
37