1 /* 2 * Copyright (c) 2019 Carlo Caione <ccaione@baylibre.com> 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 /** 8 * @file 9 * @brief Cortex-A public interrupt handling 10 * 11 * ARM64-specific kernel interrupt handling interface. 12 * Included by arm64/arch.h. 13 */ 14 15 #ifndef ZEPHYR_INCLUDE_ARCH_ARM64_IRQ_H_ 16 #define ZEPHYR_INCLUDE_ARCH_ARM64_IRQ_H_ 17 18 #include <irq.h> 19 #include <sw_isr_table.h> 20 #include <stdbool.h> 21 22 #ifdef __cplusplus 23 extern "C" { 24 #endif 25 26 #ifdef _ASMLANGUAGE 27 GTEXT(arch_irq_enable) 28 GTEXT(arch_irq_disable) 29 GTEXT(arch_irq_is_enabled) 30 #if defined(CONFIG_ARM_CUSTOM_INTERRUPT_CONTROLLER) 31 GTEXT(z_soc_irq_get_active) 32 GTEXT(z_soc_irq_eoi) 33 #endif /* CONFIG_ARM_CUSTOM_INTERRUPT_CONTROLLER */ 34 #else 35 36 #if !defined(CONFIG_ARM_CUSTOM_INTERRUPT_CONTROLLER) 37 38 extern void arch_irq_enable(unsigned int irq); 39 extern void arch_irq_disable(unsigned int irq); 40 extern int arch_irq_is_enabled(unsigned int irq); 41 42 /* internal routine documented in C file, needed by IRQ_CONNECT() macro */ 43 extern void z_arm64_irq_priority_set(unsigned int irq, unsigned int prio, 44 uint32_t flags); 45 46 #else 47 48 /* 49 * When a custom interrupt controller is specified, map the architecture 50 * interrupt control functions to the SoC layer interrupt control functions. 51 */ 52 53 void z_soc_irq_init(void); 54 void z_soc_irq_enable(unsigned int irq); 55 void z_soc_irq_disable(unsigned int irq); 56 int z_soc_irq_is_enabled(unsigned int irq); 57 58 void z_soc_irq_priority_set( 59 unsigned int irq, unsigned int prio, unsigned int flags); 60 61 unsigned int z_soc_irq_get_active(void); 62 void z_soc_irq_eoi(unsigned int irq); 63 64 #define arch_irq_enable(irq) z_soc_irq_enable(irq) 65 #define arch_irq_disable(irq) z_soc_irq_disable(irq) 66 #define arch_irq_is_enabled(irq) z_soc_irq_is_enabled(irq) 67 68 #define z_arm64_irq_priority_set(irq, prio, flags) \ 69 z_soc_irq_priority_set(irq, prio, flags) 70 71 #endif /* !CONFIG_ARM_CUSTOM_INTERRUPT_CONTROLLER */ 72 73 extern void z_arm64_interrupt_init(void); 74 75 /* All arguments must be computable by the compiler at build time. 76 * 77 * Z_ISR_DECLARE will populate the .intList section with the interrupt's 78 * parameters, which will then be used by gen_irq_tables.py to create 79 * the vector table and the software ISR table. This is all done at 80 * build-time. 81 * 82 * We additionally set the priority in the interrupt controller at 83 * runtime. 84 */ 85 #define ARCH_IRQ_CONNECT(irq_p, priority_p, isr_p, isr_param_p, flags_p) \ 86 { \ 87 Z_ISR_DECLARE(irq_p, 0, isr_p, isr_param_p); \ 88 z_arm64_irq_priority_set(irq_p, priority_p, flags_p); \ 89 } 90 91 #define ARCH_IRQ_DIRECT_CONNECT(irq_p, priority_p, isr_p, flags_p) \ 92 { \ 93 Z_ISR_DECLARE(irq_p, ISR_FLAG_DIRECT, isr_p, NULL); \ 94 z_arm64_irq_priority_set(irq_p, priority_p, flags_p); \ 95 } 96 97 /* Spurious interrupt handler. Throws an error if called */ 98 extern void z_irq_spurious(const void *unused); 99 100 #ifdef CONFIG_GEN_SW_ISR_TABLE 101 /* Architecture-specific common entry point for interrupts from the vector 102 * table. Most likely implemented in assembly. Looks up the correct handler 103 * and parameter from the _sw_isr_table and executes it. 104 */ 105 extern void _isr_wrapper(void); 106 #endif 107 108 #endif /* _ASMLANGUAGE */ 109 110 #ifdef __cplusplus 111 } 112 #endif 113 114 #endif /* ZEPHYR_INCLUDE_ARCH_ARM64_IRQ_H_ */ 115
