1 /* 2 * Copyright (c) 2017 Intel Corporation 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 /** 8 * @file 9 * @brief Per-arch thread definition 10 * 11 * This file contains definitions for 12 * 13 * struct _thread_arch 14 * struct _callee_saved 15 * 16 * necessary to instantiate instances of struct k_thread. 17 */ 18 19 #ifndef ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_THREAD_H_ 20 #define ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_THREAD_H_ 21 22 #ifndef _ASMLANGUAGE 23 #include <zephyr/types.h> 24 25 struct _callee_saved { 26 uint32_t v1; /* r4 */ 27 uint32_t v2; /* r5 */ 28 uint32_t v3; /* r6 */ 29 uint32_t v4; /* r7 */ 30 uint32_t v5; /* r8 */ 31 uint32_t v6; /* r9 */ 32 uint32_t v7; /* r10 */ 33 uint32_t v8; /* r11 */ 34 uint32_t psp; /* r13 */ 35 }; 36 37 typedef struct _callee_saved _callee_saved_t; 38 39 #if defined(CONFIG_FPU) && defined(CONFIG_FPU_SHARING) 40 struct _preempt_float { 41 float s16; 42 float s17; 43 float s18; 44 float s19; 45 float s20; 46 float s21; 47 float s22; 48 float s23; 49 float s24; 50 float s25; 51 float s26; 52 float s27; 53 float s28; 54 float s29; 55 float s30; 56 float s31; 57 }; 58 #endif 59 60 struct _thread_arch { 61 62 /* interrupt locking key */ 63 uint32_t basepri; 64 65 /* r0 in stack frame cannot be written to reliably */ 66 uint32_t swap_return_value; 67 68 #if defined(CONFIG_FPU) && defined(CONFIG_FPU_SHARING) 69 /* 70 * No cooperative floating point register set structure exists for 71 * the Cortex-M as it automatically saves the necessary registers 72 * in its exception stack frame. 73 */ 74 struct _preempt_float preempt_float; 75 #endif 76 77 #if defined(CONFIG_ARM_STORE_EXC_RETURN) || defined(CONFIG_USERSPACE) 78 /* 79 * Status variable holding several thread status flags 80 * as follows: 81 * 82 * byte 0 83 * +-bits 4-7-----bit-3----------bit-2--------bit-1---+----bit-0------+ 84 * : | | | | | 85 * : reserved |<Guard FLOAT>| reserved | reserved | <priv mode> | 86 * : bits | | | | CONTROL.nPRIV | 87 * +------------------------------------------------------------------+ 88 * 89 * byte 1 90 * +----------------------------bits 8-15-----------------------------+ 91 * : Least significant byte of EXC_RETURN | 92 * : bit 15| bit 14| bit 13 | bit 12| bit 11 | bit 10 | bit 9 | bit 8 | 93 * : Res | S | DCRS | FType | Mode | SPSel | Res | ES | 94 * +------------------------------------------------------------------+ 95 * 96 * Bit 0: thread's current privileged mode (Supervisor or User mode) 97 * Mirrors CONTROL.nPRIV flag. 98 * Bit 2: Deprecated in favor of FType. Note: FType = !CONTROL.FPCA. 99 * indicating whether the thread has an active FP context. 100 * Mirrors CONTROL.FPCA flag. 101 * Bit 3: indicating whether the thread is applying the long (FLOAT) 102 * or the default MPU stack guard size. 103 * 104 * Bits 8-15: Least significant octet of the EXC_RETURN value when a 105 * thread is switched-out. The value is copied from LR when 106 * entering the PendSV handler. When the thread is 107 * switched in again, the value is restored to LR before 108 * exiting the PendSV handler. 109 */ 110 union { 111 uint32_t mode; 112 113 #if defined(CONFIG_ARM_STORE_EXC_RETURN) 114 struct { 115 uint8_t mode_bits; 116 uint8_t mode_exc_return; 117 uint16_t mode_reserved2; 118 }; 119 #endif 120 }; 121 122 #if defined(CONFIG_USERSPACE) 123 uint32_t priv_stack_start; 124 #if defined(CONFIG_CPU_CORTEX_R) 125 uint32_t priv_stack_end; 126 uint32_t sp_usr; 127 #endif 128 #endif 129 #endif 130 }; 131 132 #if defined(CONFIG_FPU_SHARING) && defined(CONFIG_MPU_STACK_GUARD) 133 #define Z_ARM_MODE_MPU_GUARD_FLOAT_Msk (1 << 3) 134 #endif 135 typedef struct _thread_arch _thread_arch_t; 136 137 #endif /* _ASMLANGUAGE */ 138 139 #endif /* ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_THREAD_H_ */ 140
