1 /* ARM AArch32 GCC specific public inline assembler functions and macros */
2
3 /*
4 * Copyright (c) 2015, Wind River Systems, Inc.
5 *
6 * SPDX-License-Identifier: Apache-2.0
7 */
8
9 /* Either public functions or macros or invoked by public functions */
10
11 #ifndef ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_ASM_INLINE_GCC_H_
12 #define ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_ASM_INLINE_GCC_H_
13
14 /*
15 * The file must not be included directly
16 * Include arch/cpu.h instead
17 */
18
19 #ifndef _ASMLANGUAGE
20
21 #include <zephyr/types.h>
22 #include <arch/arm/aarch32/exc.h>
23 #include <irq.h>
24
25 #if defined(CONFIG_CPU_CORTEX_R)
26 #include <arch/arm/aarch32/cortex_a_r/cpu.h>
27 #endif
28
29 #ifdef __cplusplus
30 extern "C" {
31 #endif
32
33 /* On ARMv7-M and ARMv8-M Mainline CPUs, this function prevents regular
34 * exceptions (i.e. with interrupt priority lower than or equal to
35 * _EXC_IRQ_DEFAULT_PRIO) from interrupting the CPU. NMI, Faults, SVC,
36 * and Zero Latency IRQs (if supported) may still interrupt the CPU.
37 *
38 * On ARMv6-M and ARMv8-M Baseline CPUs, this function reads the value of
39 * PRIMASK which shows if interrupts are enabled, then disables all interrupts
40 * except NMI.
41 */
42
arch_irq_lock(void)43 static ALWAYS_INLINE unsigned int arch_irq_lock(void)
44 {
45 unsigned int key;
46
47 #if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
48 __asm__ volatile("mrs %0, PRIMASK;"
49 "cpsid i"
50 : "=r" (key)
51 :
52 : "memory");
53 #elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
54 unsigned int tmp;
55
56 __asm__ volatile(
57 "mov %1, %2;"
58 "mrs %0, BASEPRI;"
59 "msr BASEPRI_MAX, %1;"
60 "isb;"
61 : "=r"(key), "=r"(tmp)
62 : "i"(_EXC_IRQ_DEFAULT_PRIO)
63 : "memory");
64 #elif defined(CONFIG_ARMV7_R)
65 __asm__ volatile(
66 "mrs %0, cpsr;"
67 "and %0, #" TOSTR(I_BIT) ";"
68 "cpsid i;"
69 : "=r" (key)
70 :
71 : "memory", "cc");
72 #else
73 #error Unknown ARM architecture
74 #endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
75
76 return key;
77 }
78
79
80 /* On Cortex-M0/M0+, this enables all interrupts if they were not
81 * previously disabled.
82 */
83
arch_irq_unlock(unsigned int key)84 static ALWAYS_INLINE void arch_irq_unlock(unsigned int key)
85 {
86 #if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
87 if (key != 0U) {
88 return;
89 }
90 __asm__ volatile(
91 "cpsie i;"
92 "isb"
93 : : : "memory");
94 #elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
95 __asm__ volatile(
96 "msr BASEPRI, %0;"
97 "isb;"
98 : : "r"(key) : "memory");
99 #elif defined(CONFIG_ARMV7_R)
100 if (key != 0U) {
101 return;
102 }
103 __asm__ volatile(
104 "cpsie i;"
105 : : : "memory", "cc");
106 #else
107 #error Unknown ARM architecture
108 #endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
109 }
110
arch_irq_unlocked(unsigned int key)111 static ALWAYS_INLINE bool arch_irq_unlocked(unsigned int key)
112 {
113 /* This convention works for both PRIMASK and BASEPRI */
114 return key == 0U;
115 }
116
117 #ifdef __cplusplus
118 }
119 #endif
120
121 #endif /* _ASMLANGUAGE */
122
123 #endif /* ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_ASM_INLINE_GCC_H_ */
124
