1/* 2 * Copyright (c) 2020 Intel Corporation. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7#include "skeleton.dtsi" 8#include <dt-bindings/interrupt-controller/intel-ioapic.h> 9#include <dt-bindings/i2c/i2c.h> 10#include <dt-bindings/pcie/pcie.h> 11 12/ { 13 cpus { 14 #address-cells = <1>; 15 #size-cells = <0>; 16 17 cpu@0 { 18 device_type = "cpu"; 19 compatible = "intel,elkhart_lake"; 20 d-cache-line-size = <64>; 21 reg = <0>; 22 }; 23 24 }; 25 26 dram0: memory@0 { 27 device_type = "memory"; 28 reg = <0x0 DT_DRAM_SIZE>; 29 }; 30 31 ibecc: ibecc { 32 compatible = "intel,ibecc"; 33 label = "ibecc"; 34 status = "okay"; 35 }; 36 37 intc: ioapic@fec00000 { 38 compatible = "intel,ioapic"; 39 reg = <0xfec00000 0x1000>; 40 interrupt-controller; 41 #interrupt-cells = <3>; 42 }; 43 44 pcie0 { 45 label = "PCIE_0"; 46 #address-cells = <1>; 47 #size-cells = <1>; 48 compatible = "intel,pcie"; 49 ranges; 50 51 uart0: uart@f000 { 52 compatible = "ns16550"; 53 54 reg = <PCIE_BDF(0,0x1e,0) PCIE_ID(0x8086,0x4b28)>; 55 56 label = "UART_0"; 57 clock-frequency = <1843200>; 58 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 59 interrupt-parent = <&intc>; 60 status = "okay"; 61 current-speed = <115200>; 62 }; 63 64 uart1: uart@f100 { 65 compatible = "ns16550"; 66 67 reg = <PCIE_BDF(0,0x1e,1) PCIE_ID(0x8086,0x4b29)>; 68 69 label = "UART_1"; 70 clock-frequency = <1843200>; 71 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 72 interrupt-parent = <&intc>; 73 74 status = "okay"; 75 current-speed = <115200>; 76 }; 77 78 uart2: uart@ca00 { 79 compatible = "ns16550"; 80 81 reg = <PCIE_BDF(0,0x19,2) PCIE_ID(0x8086,0x4b4d)>; 82 83 label = "UART_2"; 84 clock-frequency = <1843200>; 85 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 86 interrupt-parent = <&intc>; 87 88 status = "okay"; 89 current-speed = <115200>; 90 }; 91 92 uart_pse_0: uart@8800 { 93 compatible = "ns16550"; 94 95 reg = <PCIE_BDF(0,0x11,0) PCIE_ID(0x8086,0x4b96)>; 96 97 label = "UART_PSE_0"; 98 clock-frequency = <1843200>; 99 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 100 interrupt-parent = <&intc>; 101 102 status = "disabled"; 103 current-speed = <115200>; 104 }; 105 106 uart_pse_1: uart@8900 { 107 compatible = "ns16550"; 108 109 reg = <PCIE_BDF(0,0x11,1) PCIE_ID(0x8086,0x4b97)>; 110 111 label = "UART_PSE_1"; 112 clock-frequency = <1843200>; 113 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 114 interrupt-parent = <&intc>; 115 116 status = "disabled"; 117 current-speed = <115200>; 118 }; 119 120 uart_pse_2: uart@8a00 { 121 compatible = "ns16550"; 122 123 reg = <PCIE_BDF(0,0x11,2) PCIE_ID(0x8086,0x4b98)>; 124 125 label = "UART_PSE_2"; 126 clock-frequency = <1843200>; 127 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 128 interrupt-parent = <&intc>; 129 130 status = "disabled"; 131 current-speed = <115200>; 132 }; 133 134 uart_pse_3: uart@8b00 { 135 compatible = "ns16550"; 136 137 reg = <PCIE_BDF(0,0x11,3) PCIE_ID(0x8086,0x4b99)>; 138 139 label = "UART_PSE_3"; 140 clock-frequency = <1843200>; 141 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 142 interrupt-parent = <&intc>; 143 144 status = "disabled"; 145 current-speed = <115200>; 146 }; 147 148 uart_pse_4: uart@8c00 { 149 compatible = "ns16550"; 150 151 reg = <PCIE_BDF(0,0x11,4) PCIE_ID(0x8086,0x4b9a)>; 152 153 label = "UART_PSE_4"; 154 clock-frequency = <1843200>; 155 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 156 interrupt-parent = <&intc>; 157 158 status = "disabled"; 159 current-speed = <115200>; 160 }; 161 162 uart_pse_5: uart@8d00 { 163 compatible = "ns16550"; 164 165 reg = <PCIE_BDF(0,0x11,5) PCIE_ID(0x8086,0x4b9b)>; 166 167 label = "UART_PSE_5"; 168 clock-frequency = <1843200>; 169 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 170 interrupt-parent = <&intc>; 171 172 status = "disabled"; 173 current-speed = <115200>; 174 }; 175 176 i2c0: i2c@a800 { 177 compatible = "snps,designware-i2c"; 178 clock-frequency = <I2C_BITRATE_STANDARD>; 179 #address-cells = <1>; 180 #size-cells = <0>; 181 reg = <PCIE_BDF(0,0x15,0) PCIE_ID(0x8086,0x4b78)>; 182 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 183 interrupt-parent = <&intc>; 184 label = "I2C_0"; 185 186 status = "okay"; 187 }; 188 189 i2c1: i2c@a900 { 190 compatible = "snps,designware-i2c"; 191 clock-frequency = <I2C_BITRATE_STANDARD>; 192 #address-cells = <1>; 193 #size-cells = <0>; 194 reg = <PCIE_BDF(0,0x15,1) PCIE_ID(0x8086,0x4b79)>; 195 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 196 interrupt-parent = <&intc>; 197 label = "I2C_1"; 198 199 status = "okay"; 200 }; 201 202 i2c2: i2c@aa00 { 203 compatible = "snps,designware-i2c"; 204 clock-frequency = <I2C_BITRATE_STANDARD>; 205 #address-cells = <1>; 206 #size-cells = <0>; 207 reg = <PCIE_BDF(0,0x15,2) PCIE_ID(0x8086,0x4b7a)>; 208 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 209 interrupt-parent = <&intc>; 210 label = "I2C_2"; 211 212 status = "okay"; 213 }; 214 215 i2c3: i2c@ab00 { 216 compatible = "snps,designware-i2c"; 217 clock-frequency = <I2C_BITRATE_STANDARD>; 218 #address-cells = <1>; 219 #size-cells = <0>; 220 reg = <PCIE_BDF(0,0x15,3) PCIE_ID(0x8086,0x4b7b)>; 221 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 222 interrupt-parent = <&intc>; 223 label = "I2C_3"; 224 225 status = "okay"; 226 }; 227 228 i2c4: i2c@c800 { 229 compatible = "snps,designware-i2c"; 230 clock-frequency = <I2C_BITRATE_STANDARD>; 231 #address-cells = <1>; 232 #size-cells = <0>; 233 reg = <PCIE_BDF(0,0x19,0) PCIE_ID(0x8086,0x4b4b)>; 234 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 235 interrupt-parent = <&intc>; 236 label = "I2C_4"; 237 238 status = "okay"; 239 }; 240 241 i2c5: i2c@c900 { 242 compatible = "snps,designware-i2c"; 243 clock-frequency = <I2C_BITRATE_STANDARD>; 244 #address-cells = <1>; 245 #size-cells = <0>; 246 reg = <PCIE_BDF(0,0x19,1) PCIE_ID(0x8086,0x4b4c)>; 247 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 248 interrupt-parent = <&intc>; 249 label = "I2C_5"; 250 251 status = "okay"; 252 }; 253 254 i2c6: i2c@8000 { 255 compatible = "snps,designware-i2c"; 256 clock-frequency = <I2C_BITRATE_STANDARD>; 257 #address-cells = <1>; 258 #size-cells = <0>; 259 reg = <PCIE_BDF(0,0x10,0) PCIE_ID(0x8086,0x4b44)>; 260 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 261 interrupt-parent = <&intc>; 262 label = "I2C_6"; 263 264 status = "okay"; 265 }; 266 267 i2c7: i2c@8100 { 268 compatible = "snps,designware-i2c"; 269 clock-frequency = <I2C_BITRATE_STANDARD>; 270 #address-cells = <1>; 271 #size-cells = <0>; 272 reg = <PCIE_BDF(0,0x10,1) PCIE_ID(0x8086,0x4b45)>; 273 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 274 interrupt-parent = <&intc>; 275 label = "I2C_7"; 276 277 status = "okay"; 278 }; 279 280 i2c_pse_0: i2c@d800 { 281 compatible = "snps,designware-i2c"; 282 clock-frequency = <I2C_BITRATE_STANDARD>; 283 #address-cells = <1>; 284 #size-cells = <0>; 285 reg = <PCIE_BDF(0,0x1b,0) PCIE_ID(0x8086,0x4bb9)>; 286 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 287 interrupt-parent = <&intc>; 288 label = "I2C_PSE_0"; 289 290 status = "okay"; 291 }; 292 293 i2c_pse_1: i2c@d900 { 294 compatible = "snps,designware-i2c"; 295 clock-frequency = <I2C_BITRATE_STANDARD>; 296 #address-cells = <1>; 297 #size-cells = <0>; 298 reg = <PCIE_BDF(0,0x1b,1) PCIE_ID(0x8086,0x4bba)>; 299 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 300 interrupt-parent = <&intc>; 301 label = "I2C_PSE_1"; 302 303 status = "okay"; 304 }; 305 306 i2c_pse_2: i2c@da00 { 307 compatible = "snps,designware-i2c"; 308 clock-frequency = <I2C_BITRATE_STANDARD>; 309 #address-cells = <1>; 310 #size-cells = <0>; 311 reg = <PCIE_BDF(0,0x1b,2) PCIE_ID(0x8086,0x4bbb)>; 312 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 313 interrupt-parent = <&intc>; 314 label = "I2C_PSE_2"; 315 316 status = "okay"; 317 }; 318 319 i2c_pse_3: i2c@db00 { 320 compatible = "snps,designware-i2c"; 321 clock-frequency = <I2C_BITRATE_STANDARD>; 322 #address-cells = <1>; 323 #size-cells = <0>; 324 reg = <PCIE_BDF(0,0x1b,3) PCIE_ID(0x8086,0x4bbc)>; 325 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 326 interrupt-parent = <&intc>; 327 label = "I2C_PSE_3"; 328 329 status = "okay"; 330 }; 331 332 i2c_pse_4: i2c@dc00 { 333 compatible = "snps,designware-i2c"; 334 clock-frequency = <I2C_BITRATE_STANDARD>; 335 #address-cells = <1>; 336 #size-cells = <0>; 337 reg = <PCIE_BDF(0,0x1b,4) PCIE_ID(0x8086,0x4bbd)>; 338 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 339 interrupt-parent = <&intc>; 340 label = "I2C_PSE_4"; 341 342 status = "okay"; 343 }; 344 345 i2c_pse_5: i2c@dd00 { 346 compatible = "snps,designware-i2c"; 347 clock-frequency = <I2C_BITRATE_STANDARD>; 348 #address-cells = <1>; 349 #size-cells = <0>; 350 reg = <PCIE_BDF(0,0x1b,5) PCIE_ID(0x8086,0x4bbe)>; 351 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 352 interrupt-parent = <&intc>; 353 label = "I2C_PSE_5"; 354 355 status = "okay"; 356 }; 357 358 i2c_pse_6: i2c@de00 { 359 compatible = "snps,designware-i2c"; 360 clock-frequency = <I2C_BITRATE_STANDARD>; 361 #address-cells = <1>; 362 #size-cells = <0>; 363 reg = <PCIE_BDF(0,0x1b,6) PCIE_ID(0x8086,0x4bbf)>; 364 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 365 interrupt-parent = <&intc>; 366 label = "I2C_PSE_6"; 367 368 status = "okay"; 369 }; 370 }; 371 372 soc { 373 #address-cells = <1>; 374 #size-cells = <1>; 375 compatible = "simple-bus"; 376 ranges; 377 378 uart1_fixed: uart@fe040000 { 379 compatible = "ns16550"; 380 381 reg = <0xfe040000 0x1000>; 382 reg-shift = <0>; 383 384 label = "UART_1_FIXED"; 385 clock-frequency = <1843200>; 386 interrupts = <3 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 387 interrupt-parent = <&intc>; 388 389 status = "disabled"; 390 current-speed = <115200>; 391 }; 392 393 uart2_fixed: uart@fe042000 { 394 compatible = "ns16550"; 395 396 reg = <0xfe042000 0x1000>; 397 reg-shift = <0>; 398 399 label = "UART_2_FIXED"; 400 clock-frequency = <1843200>; 401 interrupts = <4 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 402 interrupt-parent = <&intc>; 403 404 status = "disabled"; 405 current-speed = <115200>; 406 }; 407 408 gpio_0_b: gpio@fd6e0700 { 409 compatible = "intel,gpio"; 410 reg = <0xfd6e0700 0x1000>; 411 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 412 interrupt-parent = <&intc>; 413 414 label = "GPIO_COM_0_B"; 415 group-index = <0x0>; 416 gpio-controller; 417 #gpio-cells = <2>; 418 419 ngpios = <24>; 420 pin-offset = <0>; 421 422 status = "okay"; 423 }; 424 425 gpio_0_t: gpio@fd6e08a0 { 426 compatible = "intel,gpio"; 427 reg = <0xfd6e08a0 0x1000>; 428 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 429 interrupt-parent = <&intc>; 430 431 label = "GPIO_COM_0_T"; 432 group-index = <0x1>; 433 gpio-controller; 434 #gpio-cells = <2>; 435 436 ngpios = <16>; 437 pin-offset = <26>; 438 439 status = "okay"; 440 }; 441 442 gpio_0_g: gpio@fd6e09a0 { 443 compatible = "intel,gpio"; 444 reg = <0xfd6e09a0 0x1000>; 445 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 446 interrupt-parent = <&intc>; 447 448 label = "GPIO_COM_0_G"; 449 group-index = <0x2>; 450 gpio-controller; 451 #gpio-cells = <2>; 452 453 ngpios = <24>; 454 pin-offset = <42>; 455 456 status = "okay"; 457 }; 458 459 gpio_1_v: gpio@fd6d0700 { 460 compatible = "intel,gpio"; 461 reg = <0xfd6d0700 0x1000>; 462 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 463 interrupt-parent = <&intc>; 464 465 label = "GPIO_COM_1_V"; 466 group-index = <0x0>; 467 gpio-controller; 468 #gpio-cells = <2>; 469 470 ngpios = <16>; 471 pin-offset = <0>; 472 473 status = "okay"; 474 }; 475 476 gpio_1_h: gpio@fd6d0800 { 477 compatible = "intel,gpio"; 478 reg = <0xfd6d0800 0x1000>; 479 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 480 interrupt-parent = <&intc>; 481 482 label = "GPIO_COM_1_H"; 483 group-index = <0x1>; 484 gpio-controller; 485 #gpio-cells = <2>; 486 487 ngpios = <24>; 488 pin-offset = <16>; 489 490 status = "okay"; 491 }; 492 493 gpio_1_d: gpio@fd6d0980 { 494 compatible = "intel,gpio"; 495 reg = <0xfd6d0980 0x1000>; 496 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 497 interrupt-parent = <&intc>; 498 499 label = "GPIO_COM_1_D"; 500 group-index = <0x2>; 501 gpio-controller; 502 #gpio-cells = <2>; 503 504 ngpios = <20>; 505 pin-offset = <40>; 506 507 status = "okay"; 508 }; 509 510 gpio_1_u: gpio@fd6d0ad0 { 511 compatible = "intel,gpio"; 512 reg = <0xfd6d0ad0 0x1000>; 513 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 514 interrupt-parent = <&intc>; 515 516 label = "GPIO_COM_1_U"; 517 group-index = <0x3>; 518 gpio-controller; 519 #gpio-cells = <2>; 520 521 ngpios = <20>; 522 pin-offset = <61>; 523 524 status = "okay"; 525 }; 526 527 gpio_1_vG: gpio@fd6d0c50 { 528 compatible = "intel,gpio"; 529 reg = <0xfd6d0c50 0x1000>; 530 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 531 interrupt-parent = <&intc>; 532 533 label = "GPIO_COM_1_vG"; 534 group-index = <0x4>; 535 gpio-controller; 536 #gpio-cells = <2>; 537 538 ngpios = <28>; 539 pin-offset = <85>; 540 541 status = "okay"; 542 }; 543 544 gpio_3_s: gpio@fd6b0810 { 545 compatible = "intel,gpio"; 546 reg = <0xfd6b0810 0x1000>; 547 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 548 interrupt-parent = <&intc>; 549 550 label = "GPIO_COM_3_S"; 551 group-index = <0x1>; 552 gpio-controller; 553 #gpio-cells = <2>; 554 555 ngpios = <2>; 556 pin-offset = <17>; 557 558 status = "okay"; 559 }; 560 561 gpio_3_a: gpio@fd6b0830 { 562 compatible = "intel,gpio"; 563 reg = <0xfd6b0830 0x1000>; 564 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 565 interrupt-parent = <&intc>; 566 567 label = "GPIO_COM_3_A"; 568 group-index = <0x2>; 569 gpio-controller; 570 #gpio-cells = <2>; 571 572 ngpios = <24>; 573 pin-offset = <25>; 574 575 status = "okay"; 576 }; 577 578 gpio_3_vG: gpio@fd6b09b0 { 579 compatible = "intel,gpio"; 580 reg = <0xfd6b09b0 0x1000>; 581 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 582 interrupt-parent = <&intc>; 583 584 label = "GPIO_COM_3_vG"; 585 group-index = <0x3>; 586 gpio-controller; 587 #gpio-cells = <2>; 588 589 ngpios = <4>; 590 pin-offset = <49>; 591 592 status = "okay"; 593 }; 594 595 gpio_4_c: gpio@fd6a0700 { 596 compatible = "intel,gpio"; 597 reg = <0xfd6a0700 0x1000>; 598 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 599 interrupt-parent = <&intc>; 600 601 label = "GPIO_COM_4_C"; 602 group-index = <0x0>; 603 gpio-controller; 604 #gpio-cells = <2>; 605 606 ngpios = <24>; 607 pin-offset = <0>; 608 609 status = "okay"; 610 }; 611 612 gpio_4_f: gpio@fd6a0880 { 613 compatible = "intel,gpio"; 614 reg = <0xfd6a0880 0x1000>; 615 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 616 interrupt-parent = <&intc>; 617 618 label = "GPIO_COM_4_F"; 619 group-index = <0x1>; 620 gpio-controller; 621 #gpio-cells = <2>; 622 623 ngpios = <24>; 624 pin-offset = <24>; 625 626 status = "okay"; 627 }; 628 629 gpio_4_e: gpio@fd6a0a70 { 630 compatible = "intel,gpio"; 631 reg = <0xfd6a0a70 0x1000>; 632 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 633 interrupt-parent = <&intc>; 634 635 label = "GPIO_COM_4_E"; 636 group-index = <0x3>; 637 gpio-controller; 638 #gpio-cells = <2>; 639 640 ngpios = <24>; 641 pin-offset = <57>; 642 643 status = "okay"; 644 }; 645 646 gpio_5_r: gpio@fd690700 { 647 compatible = "intel,gpio"; 648 reg = <0xfd690700 0x1000>; 649 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 650 interrupt-parent = <&intc>; 651 652 label = "GPIO_COM_5_R"; 653 group-index = <0x0>; 654 gpio-controller; 655 #gpio-cells = <2>; 656 657 ngpios = <8>; 658 pin-offset = <0>; 659 660 status = "okay"; 661 }; 662 663 hpet: hpet@fed00000 { 664 label = "HPET"; 665 compatible = "intel,hpet"; 666 reg = <0xfed00000 0x400>; 667 interrupts = <2 IRQ_TYPE_FIXED_EDGE_RISING 4>; 668 interrupt-parent = <&intc>; 669 670 status = "okay"; 671 }; 672 }; 673}; 674
