1/* 2 * Copyright (c) 2017-2019 Intel Corporation. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7#include "skeleton.dtsi" 8#include <dt-bindings/interrupt-controller/intel-ioapic.h> 9#include <dt-bindings/i2c/i2c.h> 10#include <dt-bindings/pcie/pcie.h> 11 12/ { 13 cpus { 14 #address-cells = <1>; 15 #size-cells = <0>; 16 17 cpu@0 { 18 device_type = "cpu"; 19 compatible = "intel,apollo_lake"; 20 d-cache-line-size = <64>; 21 reg = <0>; 22 }; 23 24 }; 25 26 dram0: memory@0 { 27 device_type = "memory"; 28 reg = <0x0 DT_DRAM_SIZE>; 29 }; 30 31 intc: ioapic@fec00000 { 32 compatible = "intel,ioapic"; 33 reg = <0xfec00000 0x1000>; 34 interrupt-controller; 35 #interrupt-cells = <3>; 36 }; 37 38 pcie0 { 39 label = "PCIE_0"; 40 #address-cells = <1>; 41 #size-cells = <1>; 42 compatible = "intel,pcie"; 43 ranges; 44 45 uart0: uart@c000 { 46 compatible = "ns16550"; 47 48 reg = <PCIE_BDF(0,0x18,0) PCIE_ID(0x8086,0x5abc)>; 49 50 label = "UART_0"; 51 clock-frequency = <1843200>; 52 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 53 interrupt-parent = <&intc>; 54 status = "okay"; 55 current-speed = <115200>; 56 }; 57 58 uart1: uart@c100 { 59 compatible = "ns16550"; 60 61 reg = <PCIE_BDF(0,0x18,1) PCIE_ID(0x8086,0x5abe)>; 62 63 label = "UART_1"; 64 clock-frequency = <1843200>; 65 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 66 interrupt-parent = <&intc>; 67 68 status = "okay"; 69 current-speed = <115200>; 70 }; 71 72 uart2: uart@c200 { 73 compatible = "ns16550"; 74 75 reg = <PCIE_BDF(0,0x18,2) PCIE_ID(0x8086,0x5ac0)>; 76 77 label = "UART_2"; 78 clock-frequency = <1843200>; 79 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 80 interrupt-parent = <&intc>; 81 82 status = "okay"; 83 current-speed = <115200>; 84 }; 85 86 uart3: uart@c300 { 87 compatible = "ns16550"; 88 89 reg = <PCIE_BDF(0,0x18,3) PCIE_ID(0x8086,0x5aee)>; 90 91 label = "UART_3"; 92 clock-frequency = <1843200>; 93 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 94 interrupt-parent = <&intc>; 95 96 status = "okay"; 97 current-speed = <115200>; 98 }; 99 100 i2c0: i2c@b000 { 101 compatible = "snps,designware-i2c"; 102 clock-frequency = <I2C_BITRATE_STANDARD>; 103 #address-cells = <1>; 104 #size-cells = <0>; 105 reg = <PCIE_BDF(0,0x16,0) PCIE_ID(0x8086,0x5aac)>; 106 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 107 interrupt-parent = <&intc>; 108 label = "I2C_0"; 109 110 status = "okay"; 111 }; 112 113 i2c1: i2c@b100 { 114 compatible = "snps,designware-i2c"; 115 clock-frequency = <I2C_BITRATE_STANDARD>; 116 #address-cells = <1>; 117 #size-cells = <0>; 118 reg = <PCIE_BDF(0,0x16,1) PCIE_ID(0x8086,0x5aae)>; 119 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 120 interrupt-parent = <&intc>; 121 label = "I2C_1"; 122 123 status = "okay"; 124 }; 125 126 i2c2: i2c@b200 { 127 compatible = "snps,designware-i2c"; 128 clock-frequency = <I2C_BITRATE_STANDARD>; 129 #address-cells = <1>; 130 #size-cells = <0>; 131 reg = <PCIE_BDF(0,0x16,2) PCIE_ID(0x8086,0x5ab0)>; 132 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 133 interrupt-parent = <&intc>; 134 label = "I2C_2"; 135 136 status = "okay"; 137 }; 138 139 i2c3: i2c@b300 { 140 compatible = "snps,designware-i2c"; 141 clock-frequency = <I2C_BITRATE_STANDARD>; 142 #address-cells = <1>; 143 #size-cells = <0>; 144 reg = <PCIE_BDF(0,0x16,3) PCIE_ID(0x8086,0x5ab2)>; 145 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 146 interrupt-parent = <&intc>; 147 label = "I2C_3"; 148 149 status = "okay"; 150 }; 151 152 i2c4: i2c@b800 { 153 compatible = "snps,designware-i2c"; 154 clock-frequency = <I2C_BITRATE_STANDARD>; 155 #address-cells = <1>; 156 #size-cells = <0>; 157 reg = <PCIE_BDF(0,0x17,0) PCIE_ID(0x8086,0x5ab4)>; 158 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 159 interrupt-parent = <&intc>; 160 label = "I2C_4"; 161 162 status = "okay"; 163 }; 164 165 i2c5: i2c@b900 { 166 compatible = "snps,designware-i2c"; 167 clock-frequency = <I2C_BITRATE_STANDARD>; 168 #address-cells = <1>; 169 #size-cells = <0>; 170 reg = <PCIE_BDF(0,0x17,1) PCIE_ID(0x8086,0x5ab6)>; 171 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 172 interrupt-parent = <&intc>; 173 label = "I2C_5"; 174 175 status = "okay"; 176 }; 177 178 i2c6: i2c@ba00 { 179 compatible = "snps,designware-i2c"; 180 clock-frequency = <I2C_BITRATE_STANDARD>; 181 #address-cells = <1>; 182 #size-cells = <0>; 183 reg = <PCIE_BDF(0,0x17,2) PCIE_ID(0x8086,0x5ab8)>; 184 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 185 interrupt-parent = <&intc>; 186 label = "I2C_6"; 187 188 status = "okay"; 189 }; 190 191 i2c7: i2c@bb00 { 192 compatible = "snps,designware-i2c"; 193 clock-frequency = <I2C_BITRATE_STANDARD>; 194 #address-cells = <1>; 195 #size-cells = <0>; 196 reg = <PCIE_BDF(0,0x17,3) PCIE_ID(0x8086,0x5aba)>; 197 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 198 interrupt-parent = <&intc>; 199 label = "I2C_7"; 200 201 status = "okay"; 202 }; 203 }; 204 205 soc { 206 #address-cells = <1>; 207 #size-cells = <1>; 208 compatible = "simple-bus"; 209 ranges; 210 211 vtd: vtd@fed65000 { 212 compatible = "intel,vt-d"; 213 214 label = "VTD_0"; 215 reg = <0xfed65000 0x1000>; 216 217 status = "disabled"; 218 }; 219 220 gpio_n_000_031: gpio@d0c50000 { 221 compatible = "intel,gpio"; 222 reg = <0xd0c50000 0x1000>; 223 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 224 interrupt-parent = <&intc>; 225 226 label = "GPIO_N_000"; 227 gpio-controller; 228 #gpio-cells = <2>; 229 230 ngpios = <32>; 231 pin-offset = <0>; 232 233 status = "okay"; 234 }; 235 236 gpio_n_032_063: gpio@d0c50001 { 237 compatible = "intel,gpio"; 238 reg = <0xd0c50001 0x1000>; 239 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 240 interrupt-parent = <&intc>; 241 242 label = "GPIO_N_032"; 243 gpio-controller; 244 #gpio-cells = <2>; 245 246 ngpios = <32>; 247 pin-offset = <32>; 248 249 status = "okay"; 250 }; 251 252 gpio_n_064_077: gpio@d0c50002 { 253 compatible = "intel,gpio"; 254 reg = <0xd0c50002 0x1000>; 255 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 256 interrupt-parent = <&intc>; 257 258 label = "GPIO_N_064"; 259 gpio-controller; 260 #gpio-cells = <2>; 261 262 ngpios = <14>; 263 pin-offset = <64>; 264 265 status = "okay"; 266 }; 267 268 gpio_nw_000_031: gpio@d0c40000 { 269 compatible = "intel,gpio"; 270 reg = <0xd0c40000 0x1000>; 271 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 272 interrupt-parent = <&intc>; 273 274 label = "GPIO_NW_000"; 275 gpio-controller; 276 #gpio-cells = <2>; 277 278 ngpios = <32>; 279 pin-offset = <0>; 280 281 status = "okay"; 282 }; 283 284 gpio_nw_032_063: gpio@d0c40001 { 285 compatible = "intel,gpio"; 286 reg = <0xd0c40001 0x1000>; 287 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 288 interrupt-parent = <&intc>; 289 290 label = "GPIO_NW_032"; 291 gpio-controller; 292 #gpio-cells = <2>; 293 294 ngpios = <32>; 295 pin-offset = <32>; 296 297 status = "okay"; 298 }; 299 300 gpio_nw_064_076: gpio@d0c40002 { 301 compatible = "intel,gpio"; 302 reg = <0xd0c40002 0x1000>; 303 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 304 interrupt-parent = <&intc>; 305 306 label = "GPIO_NW_064"; 307 gpio-controller; 308 #gpio-cells = <2>; 309 310 ngpios = <13>; 311 pin-offset = <64>; 312 313 status = "okay"; 314 }; 315 316 gpio_w_000_031: gpio@d0c70000 { 317 compatible = "intel,gpio"; 318 reg = <0xd0c70000 0x1000>; 319 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 320 interrupt-parent = <&intc>; 321 322 label = "GPIO_W_000"; 323 gpio-controller; 324 #gpio-cells = <2>; 325 326 ngpios = <32>; 327 pin-offset = <0>; 328 329 status = "okay"; 330 }; 331 332 gpio_w_032_046: gpio@d0c70001 { 333 compatible = "intel,gpio"; 334 reg = <0xd0c70001 0x1000>; 335 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 336 interrupt-parent = <&intc>; 337 338 label = "GPIO_W_032"; 339 gpio-controller; 340 #gpio-cells = <2>; 341 342 ngpios = <15>; 343 pin-offset = <32>; 344 345 status = "okay"; 346 }; 347 348 gpio_sw_000_031: gpio@d0c00000 { 349 compatible = "intel,gpio"; 350 reg = <0xd0c00000 0x1000>; 351 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 352 interrupt-parent = <&intc>; 353 354 label = "GPIO_SW_000"; 355 gpio-controller; 356 #gpio-cells = <2>; 357 358 ngpios = <32>; 359 pin-offset = <0>; 360 361 status = "okay"; 362 }; 363 364 365 gpio_sw_032_042: gpio@d0c00001 { 366 compatible = "intel,gpio"; 367 reg = <0xd0c00001 0x1000>; 368 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 369 interrupt-parent = <&intc>; 370 371 label = "GPIO_SW_032"; 372 gpio-controller; 373 #gpio-cells = <2>; 374 375 ngpios = <11>; 376 pin-offset = <32>; 377 378 status = "okay"; 379 }; 380 381 hpet: hpet@fed00000 { 382 label = "HPET"; 383 compatible = "intel,hpet"; 384 reg = <0xfed00000 0x400>; 385 interrupts = <2 IRQ_TYPE_FIXED_EDGE_RISING 4>; 386 interrupt-parent = <&intc>; 387 388 status = "okay"; 389 }; 390 }; 391 392 gpio_n: gpio-north { 393 /* n north 78 */ 394 compatible = "intel,apollo-lake-gpio"; 395 #gpio-cells = <2>; 396 gpio-map-mask = <0xffffffff 0xffffffc0>; 397 gpio-map-pass-thru = <0 0x3f>; 398 gpio-map = 399 <0 0 &gpio_n_000_031 0 0>, 400 <1 0 &gpio_n_000_031 1 0>, 401 <2 0 &gpio_n_000_031 2 0>, 402 <3 0 &gpio_n_000_031 3 0>, 403 <4 0 &gpio_n_000_031 4 0>, 404 <5 0 &gpio_n_000_031 5 0>, 405 <6 0 &gpio_n_000_031 6 0>, 406 <7 0 &gpio_n_000_031 7 0>, 407 <8 0 &gpio_n_000_031 8 0>, 408 <9 0 &gpio_n_000_031 9 0>, 409 <10 0 &gpio_n_000_031 10 0>, 410 <11 0 &gpio_n_000_031 11 0>, 411 <12 0 &gpio_n_000_031 12 0>, 412 <13 0 &gpio_n_000_031 13 0>, 413 <14 0 &gpio_n_000_031 14 0>, 414 <15 0 &gpio_n_000_031 15 0>, 415 <16 0 &gpio_n_000_031 16 0>, 416 <17 0 &gpio_n_000_031 17 0>, 417 <18 0 &gpio_n_000_031 18 0>, 418 <19 0 &gpio_n_000_031 19 0>, 419 <20 0 &gpio_n_000_031 20 0>, 420 <21 0 &gpio_n_000_031 21 0>, 421 <22 0 &gpio_n_000_031 22 0>, 422 <23 0 &gpio_n_000_031 23 0>, 423 <24 0 &gpio_n_000_031 24 0>, 424 <25 0 &gpio_n_000_031 25 0>, 425 <26 0 &gpio_n_000_031 26 0>, 426 <27 0 &gpio_n_000_031 27 0>, 427 <28 0 &gpio_n_000_031 28 0>, 428 <29 0 &gpio_n_000_031 29 0>, 429 <30 0 &gpio_n_000_031 30 0>, 430 <31 0 &gpio_n_000_031 31 0>, 431 <32 0 &gpio_n_032_063 0 0>, 432 <33 0 &gpio_n_032_063 1 0>, 433 <34 0 &gpio_n_032_063 2 0>, 434 <35 0 &gpio_n_032_063 3 0>, 435 <36 0 &gpio_n_032_063 4 0>, 436 <37 0 &gpio_n_032_063 5 0>, 437 <38 0 &gpio_n_032_063 6 0>, 438 <39 0 &gpio_n_032_063 7 0>, 439 <40 0 &gpio_n_032_063 8 0>, 440 <41 0 &gpio_n_032_063 9 0>, 441 <42 0 &gpio_n_032_063 10 0>, 442 <43 0 &gpio_n_032_063 11 0>, 443 <44 0 &gpio_n_032_063 12 0>, 444 <45 0 &gpio_n_032_063 13 0>, 445 <46 0 &gpio_n_032_063 14 0>, 446 <47 0 &gpio_n_032_063 15 0>, 447 <48 0 &gpio_n_032_063 16 0>, 448 <49 0 &gpio_n_032_063 17 0>, 449 <50 0 &gpio_n_032_063 18 0>, 450 <51 0 &gpio_n_032_063 19 0>, 451 <52 0 &gpio_n_032_063 20 0>, 452 <53 0 &gpio_n_032_063 21 0>, 453 <54 0 &gpio_n_032_063 22 0>, 454 <55 0 &gpio_n_032_063 23 0>, 455 <56 0 &gpio_n_032_063 24 0>, 456 <57 0 &gpio_n_032_063 25 0>, 457 <58 0 &gpio_n_032_063 26 0>, 458 <59 0 &gpio_n_032_063 27 0>, 459 <60 0 &gpio_n_032_063 28 0>, 460 <61 0 &gpio_n_032_063 29 0>, 461 <62 0 &gpio_n_032_063 30 0>, 462 <63 0 &gpio_n_032_063 31 0>, 463 <64 0 &gpio_n_064_077 0 0>, 464 <65 0 &gpio_n_064_077 1 0>, 465 <66 0 &gpio_n_064_077 2 0>, 466 <67 0 &gpio_n_064_077 3 0>, 467 <68 0 &gpio_n_064_077 4 0>, 468 <69 0 &gpio_n_064_077 5 0>, 469 <70 0 &gpio_n_064_077 6 0>, 470 <71 0 &gpio_n_064_077 7 0>, 471 <72 0 &gpio_n_064_077 8 0>, 472 <73 0 &gpio_n_064_077 9 0>, 473 <74 0 &gpio_n_064_077 10 0>, 474 <75 0 &gpio_n_064_077 11 0>, 475 <76 0 &gpio_n_064_077 12 0>, 476 <77 0 &gpio_n_064_077 13 0>; 477 }; 478 479 gpio_nw: gpio-northwest { 480 /* nw northwest 77 */ 481 compatible = "intel,apollo-lake-gpio"; 482 #gpio-cells = <2>; 483 gpio-map-mask = <0xffffffff 0xffffffc0>; 484 gpio-map-pass-thru = <0 0x3f>; 485 gpio-map = 486 <0 0 &gpio_nw_000_031 0 0>, 487 <1 0 &gpio_nw_000_031 1 0>, 488 <2 0 &gpio_nw_000_031 2 0>, 489 <3 0 &gpio_nw_000_031 3 0>, 490 <4 0 &gpio_nw_000_031 4 0>, 491 <5 0 &gpio_nw_000_031 5 0>, 492 <6 0 &gpio_nw_000_031 6 0>, 493 <7 0 &gpio_nw_000_031 7 0>, 494 <8 0 &gpio_nw_000_031 8 0>, 495 <9 0 &gpio_nw_000_031 9 0>, 496 <10 0 &gpio_nw_000_031 10 0>, 497 <11 0 &gpio_nw_000_031 11 0>, 498 <12 0 &gpio_nw_000_031 12 0>, 499 <13 0 &gpio_nw_000_031 13 0>, 500 <14 0 &gpio_nw_000_031 14 0>, 501 <15 0 &gpio_nw_000_031 15 0>, 502 <16 0 &gpio_nw_000_031 16 0>, 503 <17 0 &gpio_nw_000_031 17 0>, 504 <18 0 &gpio_nw_000_031 18 0>, 505 <19 0 &gpio_nw_000_031 19 0>, 506 <20 0 &gpio_nw_000_031 20 0>, 507 <21 0 &gpio_nw_000_031 21 0>, 508 <22 0 &gpio_nw_000_031 22 0>, 509 <23 0 &gpio_nw_000_031 23 0>, 510 <24 0 &gpio_nw_000_031 24 0>, 511 <25 0 &gpio_nw_000_031 25 0>, 512 <26 0 &gpio_nw_000_031 26 0>, 513 <27 0 &gpio_nw_000_031 27 0>, 514 <28 0 &gpio_nw_000_031 28 0>, 515 <29 0 &gpio_nw_000_031 29 0>, 516 <30 0 &gpio_nw_000_031 30 0>, 517 <31 0 &gpio_nw_000_031 31 0>, 518 <32 0 &gpio_nw_032_063 0 0>, 519 <33 0 &gpio_nw_032_063 1 0>, 520 <34 0 &gpio_nw_032_063 2 0>, 521 <35 0 &gpio_nw_032_063 3 0>, 522 <36 0 &gpio_nw_032_063 4 0>, 523 <37 0 &gpio_nw_032_063 5 0>, 524 <38 0 &gpio_nw_032_063 6 0>, 525 <39 0 &gpio_nw_032_063 7 0>, 526 <40 0 &gpio_nw_032_063 8 0>, 527 <41 0 &gpio_nw_032_063 9 0>, 528 <42 0 &gpio_nw_032_063 10 0>, 529 <43 0 &gpio_nw_032_063 11 0>, 530 <44 0 &gpio_nw_032_063 12 0>, 531 <45 0 &gpio_nw_032_063 13 0>, 532 <46 0 &gpio_nw_032_063 14 0>, 533 <47 0 &gpio_nw_032_063 15 0>, 534 <48 0 &gpio_nw_032_063 16 0>, 535 <49 0 &gpio_nw_032_063 17 0>, 536 <50 0 &gpio_nw_032_063 18 0>, 537 <51 0 &gpio_nw_032_063 19 0>, 538 <52 0 &gpio_nw_032_063 20 0>, 539 <53 0 &gpio_nw_032_063 21 0>, 540 <54 0 &gpio_nw_032_063 22 0>, 541 <55 0 &gpio_nw_032_063 23 0>, 542 <56 0 &gpio_nw_032_063 24 0>, 543 <57 0 &gpio_nw_032_063 25 0>, 544 <58 0 &gpio_nw_032_063 26 0>, 545 <59 0 &gpio_nw_032_063 27 0>, 546 <60 0 &gpio_nw_032_063 28 0>, 547 <61 0 &gpio_nw_032_063 29 0>, 548 <62 0 &gpio_nw_032_063 30 0>, 549 <63 0 &gpio_nw_032_063 31 0>, 550 <64 0 &gpio_nw_064_076 0 0>, 551 <65 0 &gpio_nw_064_076 1 0>, 552 <66 0 &gpio_nw_064_076 2 0>, 553 <67 0 &gpio_nw_064_076 3 0>, 554 <68 0 &gpio_nw_064_076 4 0>, 555 <69 0 &gpio_nw_064_076 5 0>, 556 <70 0 &gpio_nw_064_076 6 0>, 557 <71 0 &gpio_nw_064_076 7 0>, 558 <72 0 &gpio_nw_064_076 8 0>, 559 <73 0 &gpio_nw_064_076 9 0>, 560 <74 0 &gpio_nw_064_076 10 0>, 561 <75 0 &gpio_nw_064_076 11 0>, 562 <76 0 &gpio_nw_064_076 12 0>; 563 }; 564 565 gpio_w: gpio-west { 566 /* w west 47 */ 567 compatible = "intel,apollo-lake-gpio"; 568 #gpio-cells = <2>; 569 gpio-map-mask = <0xffffffff 0xffffffc0>; 570 gpio-map-pass-thru = <0 0x3f>; 571 gpio-map = 572 <0 0 &gpio_w_000_031 0 0>, 573 <1 0 &gpio_w_000_031 1 0>, 574 <2 0 &gpio_w_000_031 2 0>, 575 <3 0 &gpio_w_000_031 3 0>, 576 <4 0 &gpio_w_000_031 4 0>, 577 <5 0 &gpio_w_000_031 5 0>, 578 <6 0 &gpio_w_000_031 6 0>, 579 <7 0 &gpio_w_000_031 7 0>, 580 <8 0 &gpio_w_000_031 8 0>, 581 <9 0 &gpio_w_000_031 9 0>, 582 <10 0 &gpio_w_000_031 10 0>, 583 <11 0 &gpio_w_000_031 11 0>, 584 <12 0 &gpio_w_000_031 12 0>, 585 <13 0 &gpio_w_000_031 13 0>, 586 <14 0 &gpio_w_000_031 14 0>, 587 <15 0 &gpio_w_000_031 15 0>, 588 <16 0 &gpio_w_000_031 16 0>, 589 <17 0 &gpio_w_000_031 17 0>, 590 <18 0 &gpio_w_000_031 18 0>, 591 <19 0 &gpio_w_000_031 19 0>, 592 <20 0 &gpio_w_000_031 20 0>, 593 <21 0 &gpio_w_000_031 21 0>, 594 <22 0 &gpio_w_000_031 22 0>, 595 <23 0 &gpio_w_000_031 23 0>, 596 <24 0 &gpio_w_000_031 24 0>, 597 <25 0 &gpio_w_000_031 25 0>, 598 <26 0 &gpio_w_000_031 26 0>, 599 <27 0 &gpio_w_000_031 27 0>, 600 <28 0 &gpio_w_000_031 28 0>, 601 <29 0 &gpio_w_000_031 29 0>, 602 <30 0 &gpio_w_000_031 30 0>, 603 <31 0 &gpio_w_000_031 31 0>, 604 <32 0 &gpio_w_032_046 0 0>, 605 <33 0 &gpio_w_032_046 1 0>, 606 <34 0 &gpio_w_032_046 2 0>, 607 <35 0 &gpio_w_032_046 3 0>, 608 <36 0 &gpio_w_032_046 4 0>, 609 <37 0 &gpio_w_032_046 5 0>, 610 <38 0 &gpio_w_032_046 6 0>, 611 <39 0 &gpio_w_032_046 7 0>, 612 <40 0 &gpio_w_032_046 8 0>, 613 <41 0 &gpio_w_032_046 9 0>, 614 <42 0 &gpio_w_032_046 10 0>, 615 <43 0 &gpio_w_032_046 11 0>, 616 <44 0 &gpio_w_032_046 12 0>, 617 <45 0 &gpio_w_032_046 13 0>, 618 <46 0 &gpio_w_032_046 14 0>; 619 }; 620 621 gpio_sw: gpio-southwest { 622 /* sw southwest 42 */ 623 compatible = "intel,apollo-lake-gpio"; 624 #gpio-cells = <2>; 625 gpio-map-mask = <0xffffffff 0xffffffc0>; 626 gpio-map-pass-thru = <0 0x3f>; 627 gpio-map = 628 <0 0 &gpio_sw_000_031 0 0>, 629 <1 0 &gpio_sw_000_031 1 0>, 630 <2 0 &gpio_sw_000_031 2 0>, 631 <3 0 &gpio_sw_000_031 3 0>, 632 <4 0 &gpio_sw_000_031 4 0>, 633 <5 0 &gpio_sw_000_031 5 0>, 634 <6 0 &gpio_sw_000_031 6 0>, 635 <7 0 &gpio_sw_000_031 7 0>, 636 <8 0 &gpio_sw_000_031 8 0>, 637 <9 0 &gpio_sw_000_031 9 0>, 638 <10 0 &gpio_sw_000_031 10 0>, 639 <11 0 &gpio_sw_000_031 11 0>, 640 <12 0 &gpio_sw_000_031 12 0>, 641 <13 0 &gpio_sw_000_031 13 0>, 642 <14 0 &gpio_sw_000_031 14 0>, 643 <15 0 &gpio_sw_000_031 15 0>, 644 <16 0 &gpio_sw_000_031 16 0>, 645 <17 0 &gpio_sw_000_031 17 0>, 646 <18 0 &gpio_sw_000_031 18 0>, 647 <19 0 &gpio_sw_000_031 19 0>, 648 <20 0 &gpio_sw_000_031 20 0>, 649 <21 0 &gpio_sw_000_031 21 0>, 650 <22 0 &gpio_sw_000_031 22 0>, 651 <23 0 &gpio_sw_000_031 23 0>, 652 <24 0 &gpio_sw_000_031 24 0>, 653 <25 0 &gpio_sw_000_031 25 0>, 654 <26 0 &gpio_sw_000_031 26 0>, 655 <27 0 &gpio_sw_000_031 27 0>, 656 <28 0 &gpio_sw_000_031 28 0>, 657 <29 0 &gpio_sw_000_031 29 0>, 658 <30 0 &gpio_sw_000_031 30 0>, 659 <31 0 &gpio_sw_000_031 31 0>, 660 <32 0 &gpio_sw_032_042 0 0>, 661 <33 0 &gpio_sw_032_042 1 0>, 662 <34 0 &gpio_sw_032_042 2 0>, 663 <35 0 &gpio_sw_032_042 3 0>, 664 <36 0 &gpio_sw_032_042 4 0>, 665 <37 0 &gpio_sw_032_042 5 0>, 666 <38 0 &gpio_sw_032_042 6 0>, 667 <39 0 &gpio_sw_032_042 7 0>, 668 <40 0 &gpio_sw_032_042 8 0>, 669 <41 0 &gpio_sw_032_042 9 0>, 670 <42 0 &gpio_sw_032_042 10 0>; 671 }; 672}; 673
