1/*
2 * Copyright (c) 2021 Telink Semiconductor
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7/dts-v1/;
8
9#include <dt-bindings/gpio/gpio.h>
10#include <dt-bindings/i2c/i2c.h>
11#include <dt-bindings/pinctrl/b91-pinctrl.h>
12
13/ {
14	#address-cells = <1>;
15	#size-cells = <1>;
16
17	cpus {
18		#address-cells = <1>;
19		#size-cells = <0>;
20		cpu0: cpu@0 {
21			reg = <0>;
22			clock-frequency = <24000000>;
23			compatible ="telink,b91", "riscv";
24		};
25	};
26
27	soc {
28		#address-cells = <1>;
29		#size-cells = <1>;
30		compatible = "telink,telink_b91-soc";
31		ranges;
32
33		ram_ilm: memory@0 {
34			compatible = "mmio-sram";
35		};
36
37		ram_dlm: memory@80000 {
38			compatible = "mmio-sram";
39		};
40
41		flash_mspi: flash-controller@80140100 {
42			compatible = "telink,b91-flash-controller";
43			label = "FLASH_MSPI";
44			reg = <0x80140100 0x40>;
45
46			#address-cells = <1>;
47			#size-cells = <1>;
48
49			flash: flash@20000000 {
50				compatible = "soc-nv-flash";
51				write-block-size = <1>;
52			};
53		};
54
55		power: power@80140180 {
56			compatible = "telink,b91-power";
57			reg = <0x80140180 0x40>;
58			power-mode = "LDO_1P4_LDO_1P8";
59			vbat-type = "VBAT_MAX_VALUE_GREATER_THAN_3V6";
60			status = "okay";
61		};
62
63		gpioa: gpio@80140300 {
64			compatible = "telink,b91-gpio";
65			gpio-controller;
66			interrupt-parent = <&plic0>;
67			interrupts = <25 1>, <26 1>, <27 1>;
68			reg = <0x80140300 0x08>;
69			label = "GPIO_A";
70			status = "disabled";
71			#gpio-cells = <2>;
72		};
73
74		gpiob: gpio@80140308 {
75			compatible = "telink,b91-gpio";
76			gpio-controller;
77			interrupt-parent = <&plic0>;
78			interrupts = <25 1>, <26 1>, <27 1>;
79			reg = <0x80140308 0x08>;
80			label = "GPIO_B";
81			status = "disabled";
82			#gpio-cells = <2>;
83		};
84
85		gpioc: gpio@80140310 {
86			compatible = "telink,b91-gpio";
87			gpio-controller;
88			interrupt-parent = <&plic0>;
89			interrupts = <25 1>, <26 1>, <27 1>;
90			reg = <0x80140310 0x08>;
91			label = "GPIO_C";
92			status = "disabled";
93			#gpio-cells = <2>;
94		};
95
96		gpiod: gpio@80140318 {
97			compatible = "telink,b91-gpio";
98			gpio-controller;
99			interrupt-parent = <&plic0>;
100			interrupts = <25 1>, <26 1>, <27 1>;
101			reg = <0x80140318 0x08>;
102			label = "GPIO_D";
103			status = "disabled";
104			#gpio-cells = <2>;
105		};
106
107		gpioe: gpio@80140320 {
108			compatible = "telink,b91-gpio";
109			gpio-controller;
110			interrupt-parent = <&plic0>;
111			interrupts = <25 1>, <26 1>, <27 1>;
112			reg = <0x80140320 0x08>;
113			label = "GPIO_E";
114			status = "disabled";
115			#gpio-cells = <2>;
116		};
117
118		plic0: interrupt-controller@e4000000 {
119			compatible = "sifive,plic-1.0.0";
120			#interrupt-cells = <2>;
121			interrupt-controller;
122			reg = < 0xe4000000 0x00001000
123					0xe4002000 0x00000800
124					0xe4200000 0x00010000 >;
125			reg-names = "prio", "irq_en", "reg";
126			riscv,max-priority = <3>;
127			riscv,ndev = <63>;
128		};
129
130		uart0: serial@80140080 {
131			compatible = "telink,b91-uart";
132			label = "UART_0";
133			reg = <0x80140080 0x40>;
134			interrupts = <19 1>;
135			interrupt-parent = <&plic0>;
136			status = "disabled";
137		};
138
139		uart1: serial@801400C0 {
140			compatible = "telink,b91-uart";
141			label = "UART_1";
142			reg = <0x801400C0 0x40>;
143			interrupts = <18 1>;
144			interrupt-parent = <&plic0>;
145			status = "disabled";
146		};
147
148		ieee802154: ieee802154@80140800 {
149			compatible = "telink,b91-zb";
150			reg = <0x80140800 0x800>;
151			label = "IEEE802154";
152			interrupt-parent = <&plic0>;
153			interrupts = <15 2>;
154			status = "disabled";
155		};
156
157		trng0: trng@80101800 {
158			compatible = "telink,b91-trng";
159			reg = <0x80101800 0x20>;
160			label = "TRNG";
161			status = "disabled";
162		};
163
164		pwm0: pwm@80140400 {
165			compatible = "telink,b91-pwm";
166			reg = <0x80140400 0x80>;
167			channels = <6>;
168			label = "PWM";
169			status = "disabled";
170			#pwm-cells = <2>;
171		};
172
173		hspi: spi@81FFFFC0 {
174			compatible = "telink,b91-spi";
175			label = "HSPI";
176			reg = <0x81FFFFC0 0x40>;
177			peripheral-id = "HSPI_MODULE";
178			cs0-pin = "0";
179			cs1-pin = "0";
180			cs2-pin = "0";
181			#address-cells = <1>;
182			#size-cells = <0>;
183			status = "disabled";
184		};
185
186		pspi: spi@80140040 {
187			compatible = "telink,b91-spi";
188			label = "PSPI";
189			reg = <0x80140040 0x40>;
190			peripheral-id = "PSPI_MODULE";
191			cs0-pin = "0";
192			cs1-pin = "0";
193			cs2-pin = "0";
194			#address-cells = <1>;
195			#size-cells = <0>;
196			status = "disabled";
197		};
198
199		i2c: i2c@80140280 {
200			compatible = "telink,b91-i2c";
201			label = "I2C";
202			reg = <0x80140280 0x40>;
203			#address-cells = <1>;
204			#size-cells = <0>;
205			status = "disabled";
206			clock-frequency = <I2C_BITRATE_STANDARD>;
207		};
208
209		pinmux: pinmux@80140330 {
210			compatible = "telink,b91-pinmux";
211			reg = <0x80140330 0x28
212				   0x80140306 0x28
213				   0x0000000e 0x0C>;
214			reg-names = "pin_mux",
215						"gpio_en",
216						"pull_up_en";
217			label = "PINMUX";
218			status = "disabled";
219
220			/* UART0: TX(PA3 PB2 PD2), RX(PA4 PB3 PD3) */
221
222			uart0_tx_pa3: uart0_tx_pa3 {
223				pinmux = <B91_PINMUX_SET(B91_FUNC_B, B91_PORT_A, B91_PIN_3)>;
224			};
225			uart0_tx_pb2: uart0_tx_pb2 {
226				pinmux = <B91_PINMUX_SET(B91_FUNC_C, B91_PORT_B, B91_PIN_2)>;
227			};
228			uart0_tx_pd2: uart0_tx_pd2 {
229				pinmux = <B91_PINMUX_SET(B91_FUNC_A, B91_PORT_D, B91_PIN_2)>;
230			};
231
232			uart0_rx_pa4: uart0_rx_pa4 {
233				pinmux = <B91_PINMUX_SET(B91_FUNC_B, B91_PORT_A, B91_PIN_4)>;
234			};
235			uart0_rx_pb3: uart0_rx_pb3 {
236				pinmux = <B91_PINMUX_SET(B91_FUNC_C, B91_PORT_B, B91_PIN_3)>;
237			};
238			uart0_rx_pd3: uart0_rx_pd3 {
239				pinmux = <B91_PINMUX_SET(B91_FUNC_A, B91_PORT_D, B91_PIN_3)>;
240			};
241
242			/* UART1: TX(PC6 PD6 PE0), RX(PC7 PD7 PE2) */
243
244			uart1_tx_pc6: uart1_tx_pc6 {
245				pinmux = <B91_PINMUX_SET(B91_FUNC_C, B91_PORT_C, B91_PIN_6)>;
246			};
247			uart1_tx_pd6: uart1_tx_pd6 {
248				pinmux = <B91_PINMUX_SET(B91_FUNC_A, B91_PORT_D, B91_PIN_6)>;
249			};
250			uart1_tx_pe0: uart1_tx_pe0 {
251				pinmux = <B91_PINMUX_SET(B91_FUNC_B, B91_PORT_E, B91_PIN_0)>;
252			};
253
254			uart1_rx_pc7: uart1_rx_pc7 {
255				pinmux = <B91_PINMUX_SET(B91_FUNC_C, B91_PORT_C, B91_PIN_7)>;
256			};
257			uart1_rx_pd7: uart1_rx_pd7 {
258				pinmux = <B91_PINMUX_SET(B91_FUNC_A, B91_PORT_D, B91_PIN_7)>;
259			};
260			uart1_rx_pe2: uart1_rx_pe2 {
261				pinmux = <B91_PINMUX_SET(B91_FUNC_B, B91_PORT_E, B91_PIN_2)>;
262			};
263
264			/* PWM Channel 0 (PB4, PC0, PE3) */
265
266			pwm_ch0_pb4: pwm_ch0_pb4 {
267				pinmux = <B91_PINMUX_SET(B91_FUNC_B, B91_PORT_B, B91_PIN_4)>;
268			};
269			pwm_ch0_pc0: pwm_ch0_pc0 {
270				pinmux = <B91_PINMUX_SET(B91_FUNC_C, B91_PORT_C, B91_PIN_0)>;
271			};
272			pwm_ch0_pe3: pwm_ch0_pe3 {
273				pinmux = <B91_PINMUX_SET(B91_FUNC_C, B91_PORT_E, B91_PIN_3)>;
274			};
275
276			/* PWM Channel 1 (PB5, PE1) */
277
278			pwm_ch1_pb5: pwm_ch1_pb5 {
279				pinmux = <B91_PINMUX_SET(B91_FUNC_C, B91_PORT_B, B91_PIN_5)>;
280			};
281			pwm_ch1_pe1: pwm_ch1_pe1 {
282				pinmux = <B91_PINMUX_SET(B91_FUNC_C, B91_PORT_E, B91_PIN_1)>;
283			};
284
285			/* PWM Channel 2 (PB7, PE2) */
286
287			pwm_ch2_pb7: pwm_ch2_pb7 {
288				pinmux = <B91_PINMUX_SET(B91_FUNC_A, B91_PORT_B, B91_PIN_7)>;
289			};
290			pwm_ch2_pe2: pwm_ch2_pe2 {
291				pinmux = <B91_PINMUX_SET(B91_FUNC_C, B91_PORT_E, B91_PIN_2)>;
292			};
293
294			/* PWM Channel 3 (PB1, PE0) */
295
296			pwm_ch3_pb1: pwm_ch3_pb1 {
297				pinmux = <B91_PINMUX_SET(B91_FUNC_C, B91_PORT_B, B91_PIN_1)>;
298			};
299			pwm_ch3_pe0: pwm_ch3_pe0 {
300				pinmux = <B91_PINMUX_SET(B91_FUNC_C, B91_PORT_E, B91_PIN_0)>;
301			};
302
303			/* PWM Channel 4 (PD7, PE4) */
304
305			pwm_ch4_pd7: pwm_ch4_pd7 {
306				pinmux = <B91_PINMUX_SET(B91_FUNC_B, B91_PORT_D, B91_PIN_7)>;
307			};
308			pwm_ch4_pe4: pwm_ch4_pe4 {
309				pinmux = <B91_PINMUX_SET(B91_FUNC_C, B91_PORT_E, B91_PIN_4)>;
310			};
311
312			/* PWM Channel 5 (PB0, PE5) */
313
314			pwm_ch5_pb0: pwm_ch5_pb0 {
315				pinmux = <B91_PINMUX_SET(B91_FUNC_C, B91_PORT_B, B91_PIN_0)>;
316			};
317			pwm_ch5_pe5: pwm_ch5_pe5 {
318				pinmux = <B91_PINMUX_SET(B91_FUNC_C, B91_PORT_E, B91_PIN_5)>;
319			};
320
321			/* PSPI: CLK(PC5, PB5, PD1), MOSI(PC7, PB7, PD3), MISO(PC6, PB6, PD2) */
322
323			pspi_clk_pc5: pspi_clk_pc5 {
324				pinmux = <B91_PINMUX_SET(B91_FUNC_A, B91_PORT_C, B91_PIN_5)>;
325			};
326			pspi_mosi_io0_pc7: pspi_mosi_io0_pc7 {
327				pinmux = <B91_PINMUX_SET(B91_FUNC_A, B91_PORT_C, B91_PIN_7)>;
328			};
329			pspi_miso_io1_pc6: pspi_miso_io1_pc6 {
330				pinmux = <B91_PINMUX_SET(B91_FUNC_A, B91_PORT_C, B91_PIN_6)>;
331			};
332
333			pspi_clk_pb5: pspi_clk_pb5 {
334				pinmux = <B91_PINMUX_SET(B91_FUNC_B, B91_PORT_B, B91_PIN_5)>;
335			};
336			pspi_mosi_io0_pb7: pspi_mosi_io0_pb7 {
337				pinmux = <B91_PINMUX_SET(B91_FUNC_B, B91_PORT_B, B91_PIN_7)>;
338			};
339			pspi_miso_io1_pb6: pspi_miso_io1_pb6 {
340				pinmux = <B91_PINMUX_SET(B91_FUNC_B, B91_PORT_B, B91_PIN_6)>;
341			};
342
343			pspi_clk_pd1: pspi_clk_pd1 {
344				pinmux = <B91_PINMUX_SET(B91_FUNC_A, B91_PORT_D, B91_PIN_1)>;
345			};
346			pspi_mosi_io0_pd3: pspi_mosi_io0_pd3 {
347				pinmux = <B91_PINMUX_SET(B91_FUNC_A, B91_PORT_D, B91_PIN_3)>;
348			};
349			pspi_miso_io1_pd2: pspi_miso_io1_pd2 {
350				pinmux = <B91_PINMUX_SET(B91_FUNC_A, B91_PORT_D, B91_PIN_2)>;
351			};
352
353			/* HSPI: CLK(PA2, PB4), MOSI(PA4, PB3), MISO(PA3, PB2) */
354
355			hspi_clk_pa2: hspi_clk_pa2 {
356				pinmux = <B91_PINMUX_SET(B91_FUNC_C, B91_PORT_A, B91_PIN_2)>;
357			};
358			hspi_mosi_io0_pa4: hspi_mosi_io0_pa4 {
359				pinmux = <B91_PINMUX_SET(B91_FUNC_C, B91_PORT_A, B91_PIN_4)>;
360			};
361			hspi_miso_io1_pa3: hspi_miso_io1_pa3 {
362				pinmux = <B91_PINMUX_SET(B91_FUNC_C, B91_PORT_A, B91_PIN_3)>;
363			};
364
365			hspi_clk_pb4: hspi_clk_pb4 {
366				pinmux = <B91_PINMUX_SET(B91_FUNC_A, B91_PORT_B, B91_PIN_4)>;
367			};
368			hspi_mosi_io0_pb3: hspi_mosi_io0_pb3 {
369				pinmux = <B91_PINMUX_SET(B91_FUNC_A, B91_PORT_B, B91_PIN_3)>;
370			};
371			hspi_miso_io1_pb2: hspi_miso_io1_pb2 {
372				pinmux = <B91_PINMUX_SET(B91_FUNC_A, B91_PORT_B, B91_PIN_2)>;
373			};
374
375			hspi_io2_pb1: hspi_io2_pb1 {
376				pinmux = <B91_PINMUX_SET(B91_FUNC_A, B91_PORT_B, B91_PIN_1)>;
377			};
378			hspi_io3_pb0: hspi_io3_pb0 {
379				pinmux = <B91_PINMUX_SET(B91_FUNC_A, B91_PORT_B, B91_PIN_0)>;
380			};
381
382			/* Define I2C pins: SCL(PB2, PC1, PE0, PE1), SDA(PB3, PC2, PE2, PE3) */
383
384			i2c_scl_pb2: i2c_scl_pb2 {
385				pinmux = <B91_PINMUX_SET(B91_FUNC_B, B91_PORT_B, B91_PIN_2)>;
386			};
387			i2c_scl_pc1: i2c_scl_pc1 {
388				pinmux = <B91_PINMUX_SET(B91_FUNC_A, B91_PORT_C, B91_PIN_1)>;
389			};
390			i2c_scl_pe0: i2c_scl_pe0 {
391				pinmux = <B91_PINMUX_SET(B91_FUNC_A, B91_PORT_E, B91_PIN_0)>;
392			};
393			i2c_scl_pe1: i2c_scl_pe1 {
394				pinmux = <B91_PINMUX_SET(B91_FUNC_A, B91_PORT_E, B91_PIN_1)>;
395			};
396
397			i2c_sda_pb3: i2c_sda_pb3 {
398				pinmux = <B91_PINMUX_SET(B91_FUNC_B, B91_PORT_B, B91_PIN_3)>;
399			};
400			i2c_sda_pc2: i2c_sda_pc2 {
401				pinmux = <B91_PINMUX_SET(B91_FUNC_A, B91_PORT_C, B91_PIN_2)>;
402			};
403			i2c_sda_pe2: i2c_sda_pe2 {
404				pinmux = <B91_PINMUX_SET(B91_FUNC_A, B91_PORT_E, B91_PIN_2)>;
405			};
406			i2c_sda_pe3: i2c_sda_pe3 {
407				pinmux = <B91_PINMUX_SET(B91_FUNC_A, B91_PORT_E, B91_PIN_3)>;
408			};
409		};
410	};
411};
412