1/*
2 * Copyright (c) 2021 Katsuhiro Suzuki
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <dt-bindings/gpio/gpio.h>
8
9/ {
10	#address-cells = <1>;
11	#size-cells = <1>;
12	compatible = "sifive,FU740-C000", "fu740-dev", "sifive-dev";
13	model = "sifive,FU740";
14
15	cpus {
16		#address-cells = <1>;
17		#size-cells = <0>;
18
19		cpu: cpu@0 {
20			compatible = "sifive,s7", "riscv";
21			device_type = "cpu";
22			reg = <0>;
23			riscv,isa = "rv64imac";
24			status = "okay";
25
26			hlic: interrupt-controller {
27				#interrupt-cells = <1>;
28				compatible = "riscv,cpu-intc";
29				interrupt-controller;
30			};
31		};
32	};
33
34	soc {
35		#address-cells = <1>;
36		#size-cells = <1>;
37		compatible = "simple-bus";
38		ranges;
39
40		modeselect: rom@1000 {
41			compatible = "sifive,modeselect0";
42			reg = <0x1000 0x1000>;
43			reg-names = "mem";
44		};
45
46		maskrom: rom@10000 {
47			compatible = "sifive,maskrom0";
48			reg = <0x10000 0x8000>;
49			reg-names = "mem";
50		};
51
52		dtim: dtim@1000000 {
53			compatible = "sifive,dtim0";
54			reg = <0x1000000 0x2000>;
55			reg-names = "mem";
56		};
57
58		clint: clint@2000000 {
59			#interrupt-cells = <1>;
60			compatible = "riscv,clint0";
61			interrupt-controller;
62			interrupts-extended = <&hlic 3 &hlic 7>;
63			reg = <0x2000000 0x10000>;
64			reg-names = "control";
65		};
66
67		l2lim: l2lim@8000000 {
68			compatible = "sifive,l2lim0";
69			reg = <0x8000000 0x200000>;
70			reg-names = "mem";
71		};
72
73
74		plic: interrupt-controller@c000000 {
75			#interrupt-cells = <2>;
76			compatible = "sifive,plic-1.0.0";
77			interrupt-controller;
78			interrupts-extended = <&hlic 11>;
79			reg = <0x0c000000 0x00002000
80			       0x0c002000 0x001fe000
81			       0x0c200000 0x03e00000>;
82			reg-names = "prio", "irq_en", "reg";
83			riscv,max-priority = <7>;
84			riscv,ndev = <52>;
85		};
86
87		uart0: serial@10010000 {
88			compatible = "sifive,uart0";
89			interrupt-parent = <&plic>;
90			interrupts = <39 1>;
91			reg = <0x10010000 0x1000>;
92			reg-names = "control";
93			label = "uart_0";
94			status = "disabled";
95		};
96
97		uart1: serial@10011000 {
98			compatible = "sifive,uart0";
99			interrupt-parent = <&plic>;
100			interrupts = <40 1>;
101			reg = <0x10011000 0x1000>;
102			reg-names = "control";
103			label = "uart_1";
104			status = "disabled";
105		};
106
107		spi0: spi@10040000 {
108			compatible = "sifive,spi0";
109			interrupt-parent = <&plic>;
110			interrupts = <41 1>;
111			reg = <0x10040000 0x1000 0x20000000 0x10000000>;
112			reg-names = "control", "mem";
113			label = "spi_0";
114			status = "disabled";
115			#address-cells = <1>;
116			#size-cells = <0>;
117		};
118
119		spi1: spi@10041000 {
120			compatible = "sifive,spi0";
121			interrupt-parent = <&plic>;
122			interrupts = <42 1>;
123			reg = <0x10041000 0x1000>;
124			reg-names = "control";
125			label = "spi_1";
126			status = "disabled";
127			#address-cells = <1>;
128			#size-cells = <0>;
129		};
130
131		spi2: spi@10050000 {
132			compatible = "sifive,spi0";
133			interrupt-parent = <&plic>;
134			interrupts = <43 1>;
135			reg = <0x10050000 0x1000>;
136			reg-names = "control";
137			label = "spi_2";
138			status = "disabled";
139			#address-cells = <1>;
140			#size-cells = <0>;
141		};
142	};
143};
144