1/*
2 * Copyright (c) 2021 Katsuhiro Suzuki
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <dt-bindings/gpio/gpio.h>
8
9/ {
10	#address-cells = <1>;
11	#size-cells = <1>;
12	compatible = "sifive,FU540-C000", "fu540-dev", "sifive-dev";
13	model = "sifive,FU540";
14
15	cpus {
16		#address-cells = <1>;
17		#size-cells = <0>;
18
19		cpu: cpu@0 {
20			compatible = "sifive,e51", "riscv";
21			device_type = "cpu";
22			reg = <0>;
23			riscv,isa = "rv64imac";
24			status = "okay";
25
26			hlic: interrupt-controller {
27				#interrupt-cells = <1>;
28				compatible = "riscv,cpu-intc";
29				interrupt-controller;
30			};
31		};
32	};
33
34	soc {
35		#address-cells = <1>;
36		#size-cells = <1>;
37		compatible = "simple-bus";
38		ranges;
39
40		modeselect: rom@1000 {
41			compatible = "sifive,modeselect0";
42			reg = <0x1000 0x1000>;
43			reg-names = "mem";
44		};
45
46		maskrom: rom@10000 {
47			compatible = "sifive,maskrom0";
48			reg = <0x10000 0x8000>;
49			reg-names = "mem";
50		};
51
52		dtim: dtim@1000000 {
53			compatible = "sifive,dtim0";
54			reg = <0x1000000 0x2000>;
55			reg-names = "mem";
56		};
57
58		itim0: itim0@1800000 {
59			compatible = "sifive,itim0";
60			reg = <0x1800000 0x2000>;
61			reg-names = "mem";
62		};
63
64		itim1: itim1@1808000 {
65			compatible = "sifive,itim0";
66			reg = <0x1808000 0x7000>;
67			reg-names = "mem";
68		};
69
70		itim2: itim2@1810000 {
71			compatible = "sifive,itim0";
72			reg = <0x1810000 0x7000>;
73			reg-names = "mem";
74		};
75
76		itim3: itim3@1818000 {
77			compatible = "sifive,itim0";
78			reg = <0x1818000 0x7000>;
79			reg-names = "mem";
80		};
81
82		itim4: itim4@1820000 {
83			compatible = "sifive,itim0";
84			reg = <0x1820000 0x7000>;
85			reg-names = "mem";
86		};
87
88		clint: clint@2000000 {
89			#interrupt-cells = <1>;
90			compatible = "riscv,clint0";
91			interrupt-controller;
92			interrupts-extended = <&hlic 3 &hlic 7>;
93			reg = <0x2000000 0x10000>;
94			reg-names = "control";
95		};
96
97		l2lim: l2lim@8000000 {
98			compatible = "sifive,l2lim0";
99			reg = <0x8000000 0x2000000>;
100			reg-names = "mem";
101		};
102
103		plic: interrupt-controller@c000000 {
104			#interrupt-cells = <2>;
105			compatible = "sifive,plic-1.0.0";
106			interrupt-controller;
107			interrupts-extended = <&hlic 11>;
108			reg = <0x0c000000 0x00002000
109			       0x0c002000 0x001fe000
110			       0x0c200000 0x03e00000>;
111			reg-names = "prio", "irq_en", "reg";
112			riscv,max-priority = <7>;
113			riscv,ndev = <52>;
114		};
115
116		uart0: serial@10010000 {
117			compatible = "sifive,uart0";
118			interrupt-parent = <&plic>;
119			interrupts = <4 1>;
120			reg = <0x10010000 0x1000>;
121			reg-names = "control";
122			label = "uart_0";
123			status = "disabled";
124		};
125
126		uart1: serial@10011000 {
127			compatible = "sifive,uart0";
128			interrupt-parent = <&plic>;
129			interrupts = <5 1>;
130			reg = <0x10011000 0x1000>;
131			reg-names = "control";
132			label = "uart_1";
133			status = "disabled";
134		};
135
136		spi0: spi@10040000 {
137			compatible = "sifive,spi0";
138			interrupt-parent = <&plic>;
139			interrupts = <51 1>;
140			reg = <0x10040000 0x1000 0x20000000 0x10000000>;
141			reg-names = "control", "mem";
142			label = "spi_0";
143			status = "disabled";
144			#address-cells = <1>;
145			#size-cells = <0>;
146		};
147
148		spi1: spi@10041000 {
149			compatible = "sifive,spi0";
150			interrupt-parent = <&plic>;
151			interrupts = <52 1>;
152			reg = <0x10041000 0x1000>;
153			reg-names = "control";
154			label = "spi_1";
155			status = "disabled";
156			#address-cells = <1>;
157			#size-cells = <0>;
158		};
159
160		spi2: spi@10050000 {
161			compatible = "sifive,spi0";
162			interrupt-parent = <&plic>;
163			interrupts = <6 1>;
164			reg = <0x10050000 0x1000>;
165			reg-names = "control";
166			label = "spi_2";
167			status = "disabled";
168			#address-cells = <1>;
169			#size-cells = <0>;
170		};
171	};
172};
173