1/*
2 * Copyright (c) 2017 Linaro Limited
3 * Copyright (c) 2019 Centaur Analytics, Inc
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8
9#include <arm/armv7-m.dtsi>
10#include <dt-bindings/clock/stm32_clock.h>
11#include <dt-bindings/i2c/i2c.h>
12#include <dt-bindings/gpio/gpio.h>
13#include <dt-bindings/pwm/pwm.h>
14#include <freq.h>
15
16/ {
17	chosen {
18		zephyr,entropy = &rng;
19		zephyr,flash-controller = &flash;
20	};
21
22	cpus {
23		#address-cells = <1>;
24		#size-cells = <0>;
25
26		cpu0: cpu@0 {
27			device_type = "cpu";
28			compatible = "arm,cortex-m4f";
29			reg = <0>;
30		};
31	};
32
33	sram0: memory@20000000 {
34		compatible = "mmio-sram";
35	};
36
37	clocks {
38		clk_hse: clk-hse {
39			#clock-cells = <0>;
40			compatible = "st,stm32-hse-clock";
41			status = "disabled";
42		};
43
44		clk_hsi: clk-hsi {
45			#clock-cells = <0>;
46			compatible = "fixed-clock";
47			clock-frequency = <DT_FREQ_M(16)>;
48			status = "disabled";
49		};
50
51		clk_msi: clk-msi {
52			#clock-cells = <0>;
53			compatible = "st,stm32-msi-clock";
54			msi-range = <6>; /* 4MHz (reset value) */
55			status = "disabled";
56		};
57
58		clk_lse: clk-lse {
59			#clock-cells = <0>;
60			compatible = "fixed-clock";
61			clock-frequency = <32768>;
62			status = "disabled";
63		};
64
65		clk_lsi: clk-lsi {
66			#clock-cells = <0>;
67			compatible = "fixed-clock";
68			clock-frequency = <DT_FREQ_K(32)>;
69			status = "disabled";
70		};
71
72		pll: pll {
73			#clock-cells = <0>;
74			compatible = "st,stm32l4-pll-clock";
75			status = "disabled";
76		};
77	};
78
79	soc {
80		flash: flash-controller@40022000 {
81			compatible = "st,stm32-flash-controller", "st,stm32l4-flash-controller";
82			label = "FLASH_CTRL";
83			reg = <0x40022000 0x400>;
84			interrupts = <4 0>;
85			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000100>;
86
87			#address-cells = <1>;
88			#size-cells = <1>;
89
90			flash0: flash@8000000 {
91				compatible = "st,stm32-nv-flash", "soc-nv-flash";
92				label = "FLASH_STM32";
93
94				write-block-size = <8>;
95				erase-block-size = <2048>;
96				/* maximum erase time(ms) for a 2K sector */
97				max-erase-time = <25>;
98			};
99		};
100
101		rcc: rcc@40021000 {
102			compatible = "st,stm32-rcc";
103			#clock-cells = <2>;
104			reg = <0x40021000 0x400>;
105		};
106
107		exti: interrupt-controller@40010400 {
108			compatible = "st,stm32-exti";
109			interrupt-controller;
110			#interrupt-cells = <1>;
111			reg = <0x40010400 0x400>;
112		};
113
114		pinctrl: pin-controller@48000000 {
115			compatible = "st,stm32-pinctrl";
116			#address-cells = <1>;
117			#size-cells = <1>;
118			reg = <0x48000000 0x2000>;
119
120			gpioa: gpio@48000000 {
121				compatible = "st,stm32-gpio";
122				gpio-controller;
123				#gpio-cells = <2>;
124				reg = <0x48000000 0x400>;
125				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000001>;
126				label = "GPIOA";
127			};
128
129			gpiob: gpio@48000400 {
130				compatible = "st,stm32-gpio";
131				gpio-controller;
132				#gpio-cells = <2>;
133				reg = <0x48000400 0x400>;
134				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000002>;
135				label = "GPIOB";
136			};
137
138			gpioc: gpio@48000800 {
139				compatible = "st,stm32-gpio";
140				gpio-controller;
141				#gpio-cells = <2>;
142				reg = <0x48000800 0x400>;
143				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000004>;
144				label = "GPIOC";
145			};
146
147			gpioh: gpio@48001c00 {
148				compatible = "st,stm32-gpio";
149				gpio-controller;
150				#gpio-cells = <2>;
151				reg = <0x48001c00 0x400>;
152				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000080>;
153				label = "GPIOH";
154			};
155		};
156
157		iwdg: watchdog@40003000 {
158			compatible = "st,stm32-watchdog";
159			reg = <0x40003000 0x400>;
160			label = "IWDG";
161			status = "disabled";
162		};
163
164		wwdg: watchdog@40002c00 {
165			compatible = "st,stm32-window-watchdog";
166			reg = <0x40002C00 0x400>;
167			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>;
168			label = "WWDG";
169			interrupts = <0 7>;
170			status = "disabled";
171		};
172
173		usart1: serial@40013800 {
174			compatible = "st,stm32-usart", "st,stm32-uart";
175			reg = <0x40013800 0x400>;
176			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00004000>;
177			interrupts = <37 0>;
178			status = "disabled";
179			label = "UART_1";
180		};
181
182		usart2: serial@40004400 {
183			compatible = "st,stm32-usart", "st,stm32-uart";
184			reg = <0x40004400 0x400>;
185			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
186			interrupts = <38 0>;
187			status = "disabled";
188			label = "UART_2";
189		};
190
191		lpuart1: serial@40008000 {
192			compatible = "st,stm32-lpuart", "st,stm32-uart";
193			reg = <0x40008000 0x400>;
194			clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000001>;
195			interrupts = <70 0>;
196			status = "disabled";
197			label = "LPUART_1";
198		};
199
200		i2c1: i2c@40005400 {
201			compatible = "st,stm32-i2c-v2";
202			clock-frequency = <I2C_BITRATE_STANDARD>;
203			#address-cells = <1>;
204			#size-cells = <0>;
205			reg = <0x40005400 0x400>;
206			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>;
207			interrupts = <31 0>, <32 0>;
208			interrupt-names = "event", "error";
209			status = "disabled";
210			label= "I2C_1";
211		};
212
213		i2c3: i2c@40005c00 {
214			compatible = "st,stm32-i2c-v2";
215			clock-frequency = <I2C_BITRATE_STANDARD>;
216			#address-cells = <1>;
217			#size-cells = <0>;
218			reg = <0x40005c00 0x400>;
219			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00800000>;
220			interrupts = <72 0>, <73 0>;
221			interrupt-names = "event", "error";
222			status = "disabled";
223			label= "I2C_3";
224		};
225
226		quadspi: quadspi@a0001000 {
227			compatible = "st,stm32-qspi";
228			#address-cells = <1>;
229			#size-cells = <0>;
230			reg = <0xa0001000 0x400>;
231			interrupts = <71 0>;
232			clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x00000100>;
233			status = "disabled";
234			label = "QUADSPI";
235		};
236
237		spi1: spi@40013000 {
238			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
239			#address-cells = <1>;
240			#size-cells = <0>;
241			reg = <0x40013000 0x400>;
242			interrupts = <35 5>;
243			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>;
244			status = "disabled";
245			label = "SPI_1";
246		};
247
248
249		timers1: timers@40012c00 {
250			compatible = "st,stm32-timers";
251			reg = <0x40012c00 0x400>;
252			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000800>;
253			interrupts = <24 0>, <25 0>, <26 0>, <27 0>;
254			interrupt-names = "brk", "up", "trgcom", "cc";
255			status = "disabled";
256			label = "TIMERS_1";
257
258			pwm {
259				compatible = "st,stm32-pwm";
260				status = "disabled";
261				st,prescaler = <0>;
262				label = "PWM_1";
263				#pwm-cells = <3>;
264			};
265		};
266
267		timers2: timers@40000000 {
268			compatible = "st,stm32-timers";
269			reg = <0x40000000 0x400>;
270			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000001>;
271			interrupts = <28 0>;
272			interrupt-names = "global";
273			status = "disabled";
274			label = "TIMERS_2";
275
276			pwm {
277				compatible = "st,stm32-pwm";
278				status = "disabled";
279				st,prescaler = <0>;
280				label = "PWM_2";
281				#pwm-cells = <3>;
282			};
283		};
284
285		timers6: timers@40001000 {
286			compatible = "st,stm32-timers";
287			reg = <0x40001000 0x400>;
288			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000010>;
289			interrupts = <54 0>;
290			interrupt-names = "global";
291			status = "disabled";
292			label = "TIMERS_6";
293
294			pwm {
295				compatible = "st,stm32-pwm";
296				status = "disabled";
297				st,prescaler = <0>;
298				label = "PWM_6";
299				#pwm-cells = <3>;
300			};
301		};
302
303		timers15: timers@40014000 {
304			compatible = "st,stm32-timers";
305			reg = <0x40014000 0x400>;
306			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00010000>;
307			interrupts = <24 0>;
308			interrupt-names = "global";
309			status = "disabled";
310			label = "TIMERS_15";
311
312			pwm {
313				compatible = "st,stm32-pwm";
314				status = "disabled";
315				st,prescaler = <0>;
316				label = "PWM_15";
317				#pwm-cells = <3>;
318			};
319		};
320
321		timers16: timers@40014400 {
322			compatible = "st,stm32-timers";
323			reg = <0x40014400 0x400>;
324			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00020000>;
325			interrupts = <25 0>;
326			interrupt-names = "global";
327			status = "disabled";
328			label = "TIMERS_16";
329
330			pwm {
331				compatible = "st,stm32-pwm";
332				status = "disabled";
333				st,prescaler = <0>;
334				label = "PWM_16";
335				#pwm-cells = <3>;
336			};
337		};
338
339		rtc: rtc@40002800 {
340			compatible = "st,stm32-rtc";
341			reg = <0x40002800 0x400>;
342			interrupts = <41 0>;
343			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>;
344			prescaler = <32768>;
345			status = "disabled";
346			label = "RTC_0";
347		};
348
349		adc1: adc@50040000 {
350			compatible = "st,stm32-adc";
351			reg = <0x50040000 0x100>;
352			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00002000>;
353			interrupts = <18 0>;
354			status = "disabled";
355			label = "ADC_1";
356			#io-channel-cells = <1>;
357		};
358
359		adc2: adc@50040100 {
360			compatible = "st,stm32-adc";
361			reg = <0x50040100 0x100>;
362			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00002000>;
363			interrupts = <18 0>;
364			status = "disabled";
365			label = "ADC_2";
366			#io-channel-cells = <1>;
367		};
368
369		dma1: dma@40020000 {
370			compatible = "st,stm32-dma-v2";
371			#dma-cells = <3>;
372			reg = <0x40020000 0x400>;
373			interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0>;
374			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x1>;
375			dma-requests = <7>;
376			status = "disabled";
377			label = "DMA_1";
378		};
379
380		dma2: dma@40020400 {
381			compatible = "st,stm32-dma-v2";
382			#dma-cells = <3>;
383			reg = <0x40020400 0x400>;
384			interrupts = <56 0 57 0 58 0 59 0 60 0 68 0 69 0>;
385			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x2>;
386			dma-requests = <7>;
387			status = "disabled";
388			label = "DMA_2";
389		};
390
391		lptim1: timers@40007c00 {
392			compatible = "st,stm32-lptim";
393			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>;
394			#address-cells = <1>;
395			#size-cells = <0>;
396			reg = <0x40007c00 0x400>;
397			interrupts = <65 1>;
398			interrupt-names = "wakeup";
399			status = "disabled";
400			label = "LPTIM_1";
401		};
402
403		rng: rng@50060800 {
404			compatible = "st,stm32-rng";
405			reg = <0x50060800 0x400>;
406			interrupts = <80 0>;
407			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00040000>;
408			status = "disabled";
409			label = "RNG";
410		};
411	};
412};
413
414&nvic {
415	arm,num-irq-priority-bits = <4>;
416};
417