1/*
2 * Copyright (c) 2020 Teslabs Engineering S.L.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <st/h7/stm32h7.dtsi>
8
9/ {
10	soc {
11		dmamux1: dmamux@40020800 {
12			dma-requests= <107>;
13		};
14	};
15
16	/* System data RAM accessible over AXI bus: AXI SRAM in D1 domain */
17	sram0: memory@24000000 {
18		reg = <0x24000000 DT_SIZE_K(512)>;
19		compatible = "mmio-sram";
20	};
21
22	/* System data RAM accessible over AHB bus: SRAM1 in D2 domain */
23	sram1: memory@30000000 {
24		reg = <0x30000000 DT_SIZE_K(128)>;
25		compatible = "mmio-sram";
26	};
27
28	/* System data RAM accessible over AHB bus: SRAM2 in D2 domain */
29	sram2: memory@30020000 {
30		compatible = "mmio-sram";
31		reg = <0x30020000 DT_SIZE_K(128)>;
32	};
33
34	/* System data RAM accessible over AHB bus: SRAM3 in D2 domain */
35	sram3: memory@30040000 {
36		compatible = "mmio-sram";
37		reg = <0x30040000 DT_SIZE_K(32)>;
38	};
39
40	/* System data RAM accessible over AHB bus: SRAM4 in D3 domain  */
41	sram4: memory@38000000 {
42		reg = <0x38000000 DT_SIZE_K(64)>;
43		compatible = "mmio-sram";
44	};
45
46	dtcm: memory@20000000 {
47		compatible = "arm,dtcm";
48		reg = <0x20000000 DT_SIZE_K(128)>;
49	};
50};
51