1/*
2 * Copyright (c) 2020 Paul M. Bendixen
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <mem.h>
8#include <st/f3/stm32f303.dtsi>
9
10/ {
11	ccm0: memory@10000000 {
12		compatible = "st,stm32-ccm";
13		reg = <0x10000000 DT_SIZE_K(16)>;
14	};
15
16	sram0: memory@20000000 {
17		reg = <0x20000000 DT_SIZE_K(64)>;
18	};
19
20	soc {
21		flash-controller@40022000 {
22			flash0: flash@8000000 {
23				reg = <0x08000000 DT_SIZE_K(512)>;
24			};
25		};
26
27		dma2: dma@40020400 {
28			compatible = "st,stm32-dma-v2bis";
29			#dma-cells = <2>;
30			reg = <0x40020400 0x400>;
31			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x2>;
32			interrupts = <56 0 57 0 58 0 59 0 60 0>;
33			status = "disabled";
34			label = "DMA_2";
35		};
36	};
37};
38