1/* 2 * Copyright (c) 2020 Henrik Brix Andersen <henrik@brixandersen.dk> 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7#include <arm/armv8-m.dtsi> 8#include <dt-bindings/clock/mcux_lpc_syscon_clock.h> 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/i2c/i2c.h> 11#include <mem.h> 12 13/ { 14 cpus { 15 #address-cells = <1>; 16 #size-cells = <0>; 17 18 cpu@0 { 19 compatible = "arm,cortex-m33f"; 20 reg = <0>; 21 #address-cells = <1>; 22 #size-cells = <1>; 23 24 mpu: mpu@e000ed90 { 25 compatible = "arm,armv8m-mpu"; 26 reg = <0xe000ed90 0x40>; 27 arm,num-mpu-regions = <8>; 28 }; 29 }; 30 }; 31}; 32 33&sram { 34 #address-cells = <1>; 35 #size-cells = <1>; 36 37 sramx: memory@4000000 { 38 compatible = "mmio-sram"; 39 reg = <0x4000000 DT_SIZE_K(16)>; 40 }; 41 42 sram0: memory@20000000 { 43 compatible = "mmio-sram"; 44 reg = <0x20000000 DT_SIZE_K(32)>; 45 }; 46 47 sram1: memory@20008000 { 48 compatible = "mmio-sram"; 49 reg = <0x20008000 DT_SIZE_K(16)>; 50 }; 51 52 sram2: memory@2000c000 { 53 compatible = "mmio-sram"; 54 reg = <0x2000c000 DT_SIZE_K(16)>; 55 }; 56 57 sram4: memory@20010000 { 58 /* Conencted to USB bus*/ 59 compatible = "mmio-sram"; 60 reg = <0x20010000 DT_SIZE_K(16)>; 61 }; 62}; 63 64&peripheral { 65 #address-cells = <1>; 66 #size-cells = <1>; 67 68 syscon: syscon@0 { 69 compatible = "nxp,lpc-syscon"; 70 reg = <0x0 0x4000>; 71 label = "SYSCON"; 72 #clock-cells = <1>; 73 }; 74 75 iap: flash-controller@34000 { 76 compatible = "nxp,lpc-iap"; 77 label = "FLASH_IAP"; 78 reg = <0x34000 0x18>; 79 #address-cells = <1>; 80 #size-cells = <1>; 81 82 flash0: flash@0 { 83 compatible = "soc-nv-flash"; 84 label = "MCUX_FLASH"; 85 reg = <0x0 DT_SIZE_K(246)>; 86 erase-block-size = <512>; 87 write-block-size = <512>; 88 }; 89 90 flash_reserved: flash@3d800 { 91 compatible = "soc-nv-flash"; 92 reg = <0x0003d800 DT_SIZE_K(10)>; 93 status = "disabled"; 94 }; 95 96 uuid: flash@9fc70 { 97 compatible = "nxp,lpc-uid"; 98 reg = <0x9fc70 0x10>; 99 }; 100 101 boot_rom: flash@3000000 { 102 compatible = "soc-nv-flash"; 103 reg = <0x3000000 DT_SIZE_K(128)>; 104 }; 105 }; 106 107 iocon: iocon@1000 { 108 compatible = "nxp,lpc-iocon"; 109 reg = <0x1000 0x100>; 110 #address-cells = <1>; 111 #size-cells = <1>; 112 ranges = <0x0 0x1000 0x100>; 113 pio0: pio0@0 { 114 compatible = "nxp,lpc-iocon-pio"; 115 reg = <0x0 0x80>; 116 }; 117 pio1: pio0@80 { 118 compatible = "nxp,lpc-iocon-pio"; 119 reg = <0x80 0x80>; 120 }; 121 }; 122 123 gpio0: gpio@0 { 124 compatible = "nxp,lpc-gpio"; 125 reg = <0x8c000 0x2488>; 126 interrupts = <4 2>,<5 2>,<6 2>,<7 2>; 127 label = "GPIO_0"; 128 gpio-controller; 129 #gpio-cells = <2>; 130 port = <0>; 131 }; 132 133 gpio1: gpio@1 { 134 compatible = "nxp,lpc-gpio"; 135 reg = <0x8c000 0x2488>; 136 interrupts = <32 2>,<33 2>,<34 2>,<35 2>; 137 label = "GPIO_1"; 138 gpio-controller; 139 #gpio-cells = <2>; 140 port = <1>; 141 }; 142 143 flexcomm0: flexcomm@86000 { 144 compatible = "nxp,lpc-flexcomm"; 145 reg = <0x86000 0x1000>; 146 interrupts = <14 0>; 147 clocks = <&syscon MCUX_FLEXCOMM0_CLK>; 148 label = "FLEXCOMM_0"; 149 status = "disabled"; 150 }; 151 152 flexcomm1: flexcomm@87000 { 153 compatible = "nxp,lpc-flexcomm"; 154 reg = <0x87000 0x1000>; 155 interrupts = <15 0>; 156 clocks = <&syscon MCUX_FLEXCOMM1_CLK>; 157 label = "FLEXCOMM_1"; 158 status = "disabled"; 159 }; 160 161 flexcomm2: flexcomm@88000 { 162 compatible = "nxp,lpc-flexcomm"; 163 reg = <0x88000 0x1000>; 164 interrupts = <16 0>; 165 clocks = <&syscon MCUX_FLEXCOMM2_CLK>; 166 label = "FLEXCOMM_2"; 167 status = "disabled"; 168 }; 169 170 flexcomm3: flexcomm@89000 { 171 compatible = "nxp,lpc-flexcomm"; 172 reg = <0x89000 0x1000>; 173 interrupts = <17 0>; 174 clocks = <&syscon MCUX_FLEXCOMM3_CLK>; 175 label = "FLEXCOMM_3"; 176 status = "disabled"; 177 }; 178 179 flexcomm4: flexcomm@8a000 { 180 compatible = "nxp,lpc-flexcomm"; 181 reg = <0x8a000 0x1000>; 182 interrupts = <18 0>; 183 clocks = <&syscon MCUX_FLEXCOMM4_CLK>; 184 label = "FLEXCOMM_4"; 185 status = "disabled"; 186 }; 187 188 flexcomm5: flexcomm@96000 { 189 compatible = "nxp,lpc-flexcomm"; 190 reg = <0x96000 0x1000>; 191 interrupts = <19 0>; 192 clocks = <&syscon MCUX_FLEXCOMM5_CLK>; 193 label = "FLEXCOMM_5"; 194 status = "disabled"; 195 }; 196 197 flexcomm6: flexcomm@97000 { 198 compatible = "nxp,lpc-flexcomm"; 199 reg = <0x97000 0x1000>; 200 interrupts = <20 0>; 201 clocks = <&syscon MCUX_FLEXCOMM6_CLK>; 202 label = "FLEXCOMM_6"; 203 status = "disabled"; 204 }; 205 206 flexcomm7: flexcomm@98000 { 207 compatible = "nxp,lpc-flexcomm"; 208 reg = <0x98000 0x1000>; 209 interrupts = <21 0>; 210 clocks = <&syscon MCUX_FLEXCOMM7_CLK>; 211 label = "FLEXCOMM_7"; 212 status = "disabled"; 213 }; 214 215 hs_lspi: spi@9f000 { 216 compatible = "nxp,lpc-spi"; 217 reg = <0x9f000 0x1000>; 218 interrupts = <59 0>; 219 clocks = <&syscon MCUX_HS_SPI_CLK>; 220 label = "HS_LSPI"; 221 status = "disabled"; 222 #address-cells = <1>; 223 #size-cells = <0>; 224 }; 225 226 rng: rng@3a000 { 227 compatible = "nxp,lpc-rng"; 228 reg = <0x3a000 0x1000>; 229 status = "okay"; 230 label = "RNG"; 231 }; 232}; 233 234&nvic { 235 arm,num-irq-priority-bits = <3>; 236}; 237
