1/*
2 * Copyright (c) 2019 Nordic Semiconductor ASA
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <arm/armv8-m.dtsi>
8#include "nrf_common.dtsi"
9
10/ {
11	cpus {
12		#address-cells = <1>;
13		#size-cells = <0>;
14
15		cpu@0 {
16			device_type = "cpu";
17			compatible = "arm,cortex-m33f";
18			reg = <0>;
19			#address-cells = <1>;
20			#size-cells = <1>;
21			swo-ref-frequency = <64000000>;
22
23			mpu: mpu@e000ed90 {
24				compatible = "arm,armv8m-mpu";
25				reg = <0xe000ed90 0x40>;
26			};
27		};
28	};
29
30	chosen {
31		zephyr,flash-controller = &flash_controller;
32	};
33
34	soc {
35		ficr: ficr@ff0000 {
36			compatible = "nordic,nrf-ficr";
37			reg = <0xff0000 0x1000>;
38			status = "okay";
39		};
40
41		uicr: uicr@ff8000 {
42			compatible = "nordic,nrf-uicr";
43			reg = <0xff8000 0x1000>;
44			status = "okay";
45		};
46
47		sram0: memory@20000000 {
48			compatible = "mmio-sram";
49		};
50
51		peripheral@50000000 {
52			#address-cells = <1>;
53			#size-cells = <1>;
54			ranges = <0x0 0x50000000 0x10000000>;
55
56			/* Common nRF5340 Application MCU
57			 * peripheral description
58			 */
59			#include "nrf5340_cpuapp_peripherals.dtsi"
60		};
61
62		/* Additional Secure peripherals */
63
64		spu: spu@50003000 {
65			compatible = "nordic,nrf-spu";
66			reg = <0x50003000 0x1000>;
67			interrupts = <3 NRF_DEFAULT_IRQ_PRIORITY>;
68			status = "okay";
69		};
70
71		/*
72		 * GPIOTE0 is always accessible as a secure peripheral,
73		 * so we give it the 'gpiote' label for use when building
74		 * code for this target.
75		 */
76		gpiote: gpiote0: gpiote@5000d000 {
77			compatible = "nordic,nrf-gpiote";
78			reg = <0x5000d000 0x1000>;
79			interrupts = <13 5>;
80			status = "disabled";
81			label = "GPIOTE_0";
82		};
83
84		cryptocell: crypto@50844000 {
85			compatible = "nordic,nrf-cc312";
86			reg = <0x50844000 0x1000>;
87			label = "CRYPTOCELL";
88			status = "okay";
89			#address-cells = <1>;
90			#size-cells = <1>;
91			cryptocell312: crypto@50845000 {
92				compatible = "arm,cryptocell-312";
93				reg = <0x50845000 0x1000>;
94				interrupts = <68 NRF_DEFAULT_IRQ_PRIORITY>;
95				label = "CRYPTOCELL312";
96			};
97		};
98	};
99};
100
101&nvic {
102	arm,num-irq-priority-bits = <3>;
103};
104
105/*
106 * Include the non-secure peripherals file here since
107 * it expects to be at the root level. This provides
108 * a node for GPIOTE1.
109 */
110#include "nrf5340_cpuapp_peripherals_ns.dtsi"
111