1/*
2 * Copyright (c) 2019 Intel Corporation
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <arm/armv7-m.dtsi>
8
9/ {
10	cpus {
11		#address-cells = <1>;
12		#size-cells = <0>;
13
14		cpu@0 {
15			device_type = "cpu";
16			compatible = "arm,cortex-m4f";
17			reg = <0>;
18		};
19	};
20
21	flash0: flash@b0000 {
22		reg = <0x000B0000 0x68000>;
23	};
24
25	sram0: memory@118000 {
26		compatible = "mmio-sram";
27		reg = <0x00118000 0x10000>;
28	};
29
30	soc {
31		uart0: uart@400f2400 {
32			compatible = "ns16550";
33			reg = <0x400f2400 0x400>;
34			interrupts = <40 0>;
35			clock-frequency = <1843200>;
36			current-speed = <38400>;
37			label = "UART_0";
38			reg-shift = <0>;
39			status = "disabled";
40		};
41		uart1: uart@400f2800 {
42			compatible = "ns16550";
43			reg = <0x400f2800 0x400>;
44			interrupts = <41 0>;
45			clock-frequency = <1843200>;
46			current-speed = <38400>;
47			label = "UART_1";
48			reg-shift = <0>;
49			status = "disabled";
50		};
51	};
52};
53
54&nvic {
55	arm,num-irq-priority-bits = <3>;
56};
57