1/*
2 * Copyright (c) 2018, Synopsys, Inc. All rights reserved.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include "skeleton.dtsi"
8
9//#include <dt-bindings/i2c/i2c.h>
10#include <dt-bindings/gpio/gpio.h>
11
12#define DT_APB_CLK_HZ	100000000
13
14/ {
15	cpus {
16		#address-cells = <1>;
17		#size-cells = <0>;
18
19		cpu@0 {
20			device_type = "cpu";
21			compatible = "snps,arcem";
22			reg = <0>;
23		};
24
25		intc: arcv2-intc {
26			compatible = "snps,arcv2-intc";
27			interrupt-controller;
28			#interrupt-cells = <2>;
29		};
30	};
31
32	iccm0: iccm@60000000 {
33		compatible = "arc,iccm";
34		reg = <0x60000000 0x20000>;
35	};
36
37	dccm0: dccm@80000000 {
38		compatible = "arc,dccm";
39		reg = <0x80000000 0x20000>;
40	};
41
42	/* this is (Psuedo SRAM), so treat it like mmio-sram */
43	sram0: memory@10000000 {
44		compatible = "mmio-sram";
45		reg = <0x10000000 0x1000000>;
46	};
47
48
49	soc {
50		#address-cells = <1>;
51		#size-cells = <1>;
52		compatible = "simple-bus";
53		ranges;
54
55
56		uart0: uart@f0004000 {
57			compatible = "ns16550";
58			clock-frequency = <DT_APB_CLK_HZ>;
59			reg = <0xf0004000 0x1000>;
60			label = "UART_0";
61			interrupt-parent = <&intc>;
62		};
63
64		gpio0: gpio@f0002000 {
65			compatible = "snps,designware-gpio";
66			reg = <0xf0002000 0xc>;
67			ngpios = <4>;
68			label = "GPIO_0";
69			interrupt-parent = <&intc>;
70			gpio-controller;
71			#gpio-cells = <2>;
72		};
73
74		gpio1: gpio@f000200c {
75			compatible = "snps,designware-gpio";
76			reg = <0xf000200c 0xc>;
77			ngpios = <8>;
78			label = "GPIO_1";
79			interrupt-parent = <&intc>;
80			interrupts = <0 1>;
81			gpio-controller;
82			#gpio-cells = <2>;
83		};
84
85	};
86};
87