1 /*
2 * Copyright (c) 2018 Intel Corporation
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6 #include <drivers/timer/system_timer.h>
7 #include <sys_clock.h>
8 #include <spinlock.h>
9 #include <soc.h>
10
11 #define CYC_PER_TICK ((uint32_t)((uint64_t)sys_clock_hw_cycles_per_sec() \
12 / (uint64_t)CONFIG_SYS_CLOCK_TICKS_PER_SEC))
13 #define MAX_CYC INT_MAX
14 #define MAX_TICKS ((MAX_CYC - CYC_PER_TICK) / CYC_PER_TICK)
15 #define MIN_DELAY 1000
16
17 #define TICKLESS IS_ENABLED(CONFIG_TICKLESS_KERNEL)
18
19 static struct k_spinlock lock;
20 static uint64_t last_count;
21
set_mtimecmp(uint64_t time)22 static void set_mtimecmp(uint64_t time)
23 {
24 #ifdef CONFIG_64BIT
25 *(volatile uint64_t *)RISCV_MTIMECMP_BASE = time;
26 #else
27 volatile uint32_t *r = (uint32_t *)RISCV_MTIMECMP_BASE;
28
29 /* Per spec, the RISC-V MTIME/MTIMECMP registers are 64 bit,
30 * but are NOT internally latched for multiword transfers. So
31 * we have to be careful about sequencing to avoid triggering
32 * spurious interrupts: always set the high word to a max
33 * value first.
34 */
35 r[1] = 0xffffffff;
36 r[0] = (uint32_t)time;
37 r[1] = (uint32_t)(time >> 32);
38 #endif
39 }
40
mtime(void)41 static uint64_t mtime(void)
42 {
43 #ifdef CONFIG_64BIT
44 return *(volatile uint64_t *)RISCV_MTIME_BASE;
45 #else
46 volatile uint32_t *r = (uint32_t *)RISCV_MTIME_BASE;
47 uint32_t lo, hi;
48
49 /* Likewise, must guard against rollover when reading */
50 do {
51 hi = r[1];
52 lo = r[0];
53 } while (r[1] != hi);
54
55 return (((uint64_t)hi) << 32) | lo;
56 #endif
57 }
58
timer_isr(const void * arg)59 static void timer_isr(const void *arg)
60 {
61 ARG_UNUSED(arg);
62
63 k_spinlock_key_t key = k_spin_lock(&lock);
64 uint64_t now = mtime();
65 uint32_t dticks = (uint32_t)((now - last_count) / CYC_PER_TICK);
66
67 last_count = now;
68
69 if (!TICKLESS) {
70 uint64_t next = last_count + CYC_PER_TICK;
71
72 if ((int64_t)(next - now) < MIN_DELAY) {
73 next += CYC_PER_TICK;
74 }
75 set_mtimecmp(next);
76 }
77
78 k_spin_unlock(&lock, key);
79 sys_clock_announce(IS_ENABLED(CONFIG_TICKLESS_KERNEL) ? dticks : 1);
80 }
81
sys_clock_driver_init(const struct device * dev)82 int sys_clock_driver_init(const struct device *dev)
83 {
84 ARG_UNUSED(dev);
85
86 IRQ_CONNECT(RISCV_MACHINE_TIMER_IRQ, 0, timer_isr, NULL, 0);
87 last_count = mtime();
88 set_mtimecmp(last_count + CYC_PER_TICK);
89 irq_enable(RISCV_MACHINE_TIMER_IRQ);
90 return 0;
91 }
92
sys_clock_set_timeout(int32_t ticks,bool idle)93 void sys_clock_set_timeout(int32_t ticks, bool idle)
94 {
95 ARG_UNUSED(idle);
96
97 #if defined(CONFIG_TICKLESS_KERNEL)
98 /* RISCV has no idle handler yet, so if we try to spin on the
99 * logic below to reset the comparator, we'll always bump it
100 * forward to the "next tick" due to MIN_DELAY handling and
101 * the interrupt will never fire! Just rely on the fact that
102 * the OS gave us the proper timeout already.
103 */
104 if (idle) {
105 return;
106 }
107
108 ticks = ticks == K_TICKS_FOREVER ? MAX_TICKS : ticks;
109 ticks = CLAMP(ticks - 1, 0, (int32_t)MAX_TICKS);
110
111 k_spinlock_key_t key = k_spin_lock(&lock);
112 uint64_t now = mtime();
113 uint32_t adj, cyc = ticks * CYC_PER_TICK;
114
115 /* Round up to next tick boundary. */
116 adj = (uint32_t)(now - last_count) + (CYC_PER_TICK - 1);
117 if (cyc <= MAX_CYC - adj) {
118 cyc += adj;
119 } else {
120 cyc = MAX_CYC;
121 }
122 cyc = (cyc / CYC_PER_TICK) * CYC_PER_TICK;
123
124 if ((int32_t)(cyc + last_count - now) < MIN_DELAY) {
125 cyc += CYC_PER_TICK;
126 }
127
128 set_mtimecmp(cyc + last_count);
129 k_spin_unlock(&lock, key);
130 #endif
131 }
132
sys_clock_elapsed(void)133 uint32_t sys_clock_elapsed(void)
134 {
135 if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
136 return 0;
137 }
138
139 k_spinlock_key_t key = k_spin_lock(&lock);
140 uint32_t ret = ((uint32_t)mtime() - (uint32_t)last_count) / CYC_PER_TICK;
141
142 k_spin_unlock(&lock, key);
143 return ret;
144 }
145
sys_clock_cycle_get_32(void)146 uint32_t sys_clock_cycle_get_32(void)
147 {
148 return (uint32_t)mtime();
149 }
150
