1# Timer driver configuration options 2 3# Copyright (c) 2014-2015 Wind River Systems, Inc. 4# Copyright (c) 2016 Cadence Design Systems, Inc. 5# Copyright (c) 2019 Intel Corp. 6# SPDX-License-Identifier: Apache-2.0 7 8menu "Timer Drivers" 9 10menuconfig APIC_TIMER 11 bool "New local APIC timer" 12 depends on X86 13 depends on LOAPIC 14 select TICKLESS_CAPABLE 15 help 16 Use the x86 local APIC in one-shot mode as the system time 17 source. NOTE: this probably isn't what you want except on 18 older or idiosyncratic hardware (or environments like qemu 19 without complete APIC emulation). Modern hardware will work 20 better with CONFIG_APIC_TSC_DEADLINE_TIMER. 21 22if APIC_TIMER 23 24config APIC_TIMER_IRQ 25 int "Local APIC timer IRQ" 26 default 24 27 help 28 This option specifies the IRQ used by the local APIC timer. 29 Note: this MUST be set to the index immediately after the 30 last IO-APIC IRQ (the timer is the first entry in the APIC 31 local vector table). This footgun is not intended to be 32 user-configurable and almost certainly should be managed via 33 a different mechanism. 34 35config APIC_TIMER_TSC 36 bool "Use invariant TSC for sys_clock_cycle_get_32()" 37 help 38 If your CPU supports invariant TSC, and you know the ratio of the 39 TSC frequency to CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC (the local APIC 40 timer frequency), then enable this for a much faster and more 41 accurate sys_clock_cycle_get_32(). 42 43if APIC_TIMER_TSC 44 45config APIC_TIMER_TSC_N 46 int "TSC to local APIC timer frequency multiplier (N)" 47 default 1 48 49config APIC_TIMER_TSC_M 50 int "TSC to local APIC timer frequency divisor (M)" 51 default 1 52 53endif # APIC_TIMER_TSC 54 55endif # APIC_TIMER 56 57config APIC_TSC_DEADLINE_TIMER 58 bool "Even newer APIC timer using TSC deadline mode" 59 depends on X86 60 select LOAPIC 61 select TICKLESS_CAPABLE 62 help 63 Extremely simple timer driver based the local APIC TSC 64 deadline capability. The use of a free-running 64 bit 65 counter with comparator eliminates almost all edge cases 66 from the handling, and the near-instruction-cycle resolution 67 permits effectively unlimited precision where needed (the 68 limit becomes the CPU time taken to execute the timing 69 logic). SMP-safe and very fast, this should be the obvious 70 choice for any x86 device with invariant TSC and TSC 71 deadline capability. 72 73config APIC_TIMER_IRQ_PRIORITY 74 int "Local APIC timer interrupt priority" 75 depends on APIC_TIMER || APIC_TSC_DEADLINE_TIMER 76 default 4 77 help 78 This option specifies the interrupt priority used by the 79 local APIC timer. 80 81config HPET_TIMER 82 bool "HPET timer" 83 select IOAPIC if X86 84 select LOAPIC if X86 85 imply TIMER_READS_ITS_FREQUENCY_AT_RUNTIME 86 select TICKLESS_CAPABLE 87 help 88 This option selects High Precision Event Timer (HPET) as a 89 system timer. 90 91menuconfig ARCV2_TIMER 92 bool "ARC Timer" 93 default y 94 depends on ARC 95 select TICKLESS_CAPABLE 96 help 97 This module implements a kernel device driver for the ARCv2 processor timer 0 98 and provides the standard "system clock driver" interfaces. 99 100config ARCV2_TIMER_IRQ_PRIORITY 101 int "ARC timer interrupt priority" 102 default 0 103 depends on ARCV2_TIMER 104 help 105 This option specifies the IRQ priority used by the ARC timer. Lower 106 values have higher priority. 107 108config ARM_ARCH_TIMER 109 bool "ARM architected timer" 110 depends on GIC 111 select ARCH_HAS_CUSTOM_BUSY_WAIT 112 select TICKLESS_CAPABLE 113 help 114 This module implements a kernel device driver for the ARM architected 115 timer which provides per-cpu timers attached to a GIC to deliver its 116 per-processor interrupts via PPIs. 117 118DT_COMPAT_ARM_V6M_SYSTICK := arm,armv6m-systick 119DT_COMPAT_ARM_V7M_SYSTICK := arm,armv7m-systick 120DT_COMPAT_ARM_V8M_SYSTICK := arm,armv8m-systick 121DT_COMPAT_ARM_V8_1M_SYSTICK := arm,armv8.1m-systick 122 123config CORTEX_M_SYSTICK 124 bool "Cortex-M SYSTICK timer" 125 depends on CPU_CORTEX_M_HAS_SYSTICK 126 default $(dt_compat_enabled,$(DT_COMPAT_ARM_V6M_SYSTICK)) || \ 127 $(dt_compat_enabled,$(DT_COMPAT_ARM_V7M_SYSTICK)) || \ 128 $(dt_compat_enabled,$(DT_COMPAT_ARM_V8M_SYSTICK)) || \ 129 $(dt_compat_enabled,$(DT_COMPAT_ARM_V8_1M_SYSTICK)) 130 select TICKLESS_CAPABLE 131 help 132 This module implements a kernel device driver for the Cortex-M processor 133 SYSTICK timer and provides the standard "system clock driver" interfaces. 134 135config ALTERA_AVALON_TIMER 136 bool "Altera Avalon Interval Timer" 137 default y 138 depends on NIOS2 139 help 140 This module implements a kernel device driver for the Altera Avalon 141 Interval Timer as described in the Embedded IP documentation, for use 142 with Nios II and possibly other Altera soft CPUs. It provides the 143 standard "system clock driver" interfaces. 144 145config ITE_IT8XXX2_TIMER 146 bool "ITE it8xxx2 timer driver" 147 depends on SOC_IT8XXX2 148 select TICKLESS_CAPABLE 149 help 150 This module implements a kernel device driver for the ITE it8xxx2 151 HW timer model 152 153config NRF_RTC_TIMER 154 bool "nRF Real Time Counter (NRF_RTC1) Timer" 155 depends on CLOCK_CONTROL 156 depends on SOC_COMPATIBLE_NRF 157 select TICKLESS_CAPABLE 158 select NRF_HW_RTC1_RESERVED 159 help 160 This module implements a kernel device driver for the nRF Real Time 161 Counter NRF_RTC1 and provides the standard "system clock driver" 162 interfaces. 163 164if NRF_RTC_TIMER 165 166config NRF_RTC_TIMER_USER_CHAN_COUNT 167 int "Additional channels that can be used" 168 default 0 169 help 170 Use nrf_rtc_timer.h API. Driver is not managing allocation of channels. 171 172choice 173 prompt "Clock startup policy" 174 default SYSTEM_CLOCK_WAIT_FOR_STABILITY 175 176config SYSTEM_CLOCK_NO_WAIT 177 bool "No wait" 178 help 179 System clock source is initiated but does not wait for clock readiness. 180 When this option is picked, system clock may not be ready when code relying 181 on kernel API is executed. Requested timeouts will be prolonged by the 182 remaining startup time. 183 184config SYSTEM_CLOCK_WAIT_FOR_AVAILABILITY 185 bool "Wait for availability" 186 help 187 System clock source initialization waits until clock is available. In some 188 systems, clock initially runs from less accurate source which has faster 189 startup time and then seamlessly switches to the target clock source when 190 it is ready. When this option is picked, system clock is available after 191 system clock driver initialization but it may be less accurate. Option is 192 equivalent to waiting for stability if clock source does not have 193 intermediate state. 194 195config SYSTEM_CLOCK_WAIT_FOR_STABILITY 196 bool "Wait for stability" 197 help 198 System clock source initialization waits until clock is stable. When this 199 option is picked, system clock is available and stable after system clock 200 driver initialization. 201 202endchoice 203 204endif # NRF_RTC_TIMER 205 206source "drivers/timer/Kconfig.stm32_lptim" 207 208config RISCV_MACHINE_TIMER 209 bool "RISCV Machine Timer" 210 depends on SOC_FAMILY_RISCV_PRIVILEGE 211 select TICKLESS_CAPABLE 212 help 213 This module implements a kernel device driver for the generic RISCV machine 214 timer driver. It provides the standard "system clock driver" interfaces. 215 216config RV32M1_LPTMR_TIMER 217 bool "RV32M1 LPTMR system timer driver" 218 default y 219 depends on SOC_OPENISA_RV32M1_RISCV32 220 depends on RV32M1_INTMUX 221 help 222 This module implements a kernel device driver for using the LPTMR 223 peripheral as the system clock. It provides the standard "system clock 224 driver" interfaces. 225 226config LITEX_TIMER 227 bool "LiteX Timer" 228 default y 229 depends on SOC_RISCV32_LITEX_VEXRISCV 230 help 231 This module implements a kernel device driver for LiteX Timer. 232 233config NATIVE_POSIX_TIMER 234 bool "(POSIX) native_posix timer driver" 235 default y 236 depends on BOARD_NATIVE_POSIX 237 select TICKLESS_CAPABLE 238 help 239 This module implements a kernel device driver for the native_posix HW timer 240 model 241 242config XTENSA_TIMER 243 bool "Xtensa timer support" 244 depends on XTENSA 245 default y 246 select TICKLESS_CAPABLE 247 help 248 Enables a system timer driver for Xtensa based on the CCOUNT 249 and CCOMPARE special registers. 250 251config ESP32C3_SYS_TIMER 252 bool "ESP32C3 sys-timer support" 253 depends on SOC_ESP32C3 254 default y 255 select TICKLESS_CAPABLE 256 help 257 This option enables the system timer driver for the Espressif ESP32C3 258 and provides the standard "system clock driver" interface. 259 260config XTENSA_TIMER_ID 261 int "System timer CCOMPAREn register index" 262 default 1 263 depends on XTENSA_TIMER 264 help 265 Index of the CCOMPARE register (and associated interrupt) 266 used for the system timer. Xtensa CPUs have hard-configured 267 interrupt priorities associated with each timer, and some of 268 them can be unmaskable (and thus not usable by OS code that 269 need synchronization, like the timer subsystem!). Choose 270 carefully. Generally you want the timer with the highest 271 priority maskable interrupt. 272 273config SAM0_RTC_TIMER 274 bool "Atmel SAM0 series RTC timer" 275 depends on SOC_FAMILY_SAM0 276 select TICKLESS_CAPABLE 277 help 278 This module implements a kernel device driver for the Atmel SAM0 279 series Real Time Counter and provides the standard "system clock 280 driver" interfaces. 281 282config MCHP_XEC_RTOS_TIMER 283 bool "Microchip XEC series RTOS timer" 284 depends on SOC_FAMILY_MEC 285 select TICKLESS_CAPABLE 286 help 287 This module implements a kernel device driver for the Microchip 288 XEC series RTOS timer and provides the standard "system clock 289 driver" interfaces. 290 291config CC13X2_CC26X2_RTC_TIMER 292 bool "TI SimpleLink CC13x2/CC26x2 RTC timer" 293 depends on SOC_SERIES_CC13X2_CC26X2 294 select TICKLESS_CAPABLE 295 help 296 This module implements a kernel device driver for the TI SimpleLink 297 CC13X2_CC26X2 series Real Time Counter and provides the standard 298 "system clock driver" interfaces. 299 300config RCAR_CMT_TIMER 301 bool "Renesas RCar cmt timer" 302 default y 303 depends on SOC_SERIES_RCAR_GEN3 304 help 305 This module implements a kernel device driver for the Renesas RCAR 306 platform provides the standard "system clock driver" interfaces. 307 If unchecked, no timer will be used. 308 309config XLNX_PSTTC_TIMER 310 bool "Xilinx PS ttc timer support" 311 default y 312 depends on SOC_XILINX_ZYNQMP 313 select TICKLESS_CAPABLE 314 help 315 This module implements a kernel device driver for the Xilinx ZynqMP 316 platform provides the standard "system clock driver" interfaces. 317 If unchecked, no timer will be used. 318 319config XLNX_PSTTC_TIMER_INDEX 320 int "Xilinx PS ttc timer index" 321 range 0 3 322 default 0 323 depends on XLNX_PSTTC_TIMER 324 help 325 This is the index of TTC timer picked to provide system clock. 326 327config CAVS_TIMER 328 bool "CAVS DSP Wall Clock Timer on Intel SoC" 329 depends on CAVS_ICTL 330 select TICKLESS_CAPABLE 331 help 332 The DSP wall clock timer is a timer driven directly by 333 external oscillator and is external to the CPU core(s). 334 It is not as fast as the internal core clock, but provides 335 a common and synchronized counter for all CPU cores (which 336 is useful for SMP). 337 338config LEON_GPTIMER 339 bool "LEON timer" 340 depends on SOC_SPARC_LEON 341 select DYNAMIC_INTERRUPTS 342 help 343 This module implements a kernel device driver for the GRLIB 344 GPTIMER which is common in LEON systems. 345 346config NPCX_ITIM_TIMER 347 bool "Nuvoton NPCX series internal 64/32-bit timers" 348 default y 349 depends on SOC_FAMILY_NPCX 350 select TICKLESS_CAPABLE 351 help 352 This module implements a kernel device driver for the Nuvoton NPCX 353 series internal 64/32-bit timers and provides the standard "system 354 clock driver" interfaces. 355 356config SYSTEM_CLOCK_DISABLE 357 bool "API to disable system clock" 358 help 359 This option enables the sys_clock_disable() API in the kernel. It is 360 needed by some subsystems (which will automatically select it), but is 361 rarely needed by applications. 362 363config TIMER_READS_ITS_FREQUENCY_AT_RUNTIME 364 bool "Timer queries its hardware to find its frequency at runtime" 365 help 366 The drivers select this option automatically when needed. Do not modify 367 this unless you have a very good reason for it. 368 369config SYSTEM_CLOCK_SLOPPY_IDLE 370 bool "Timer allowed to skew uptime clock during idle" 371 help 372 When true, the timer driver is not required to maintain a 373 correct system uptime count when the system enters idle. 374 Some platforms may take advantage of this to reduce the 375 overhead from regular interrupts required to handle counter 376 wraparound conditions. 377 378config SYSTEM_CLOCK_INIT_PRIORITY 379 int "System clock driver initialization priority" 380 default 0 381 help 382 This options can be used to set a specific initialization priority 383 value for the system clock driver. As driver initialization might need 384 the clock to be running already, you should let the default value as it 385 is (0). 386 387# Hidden option to be selected by individual SoC. 388config TICKLESS_CAPABLE 389 bool 390 help 391 Timer drivers should select this flag if they are capable of 392 supporting tickless operation. That is, a call to 393 sys_clock_set_timeout() with a number of ticks greater than 394 one should be expected not to produce a call to 395 sys_clock_announce() (really, not to produce an interrupt at 396 all) until the specified expiration. 397 398DT_COMPAT_NXP_OS_TIMER := nxp,os-timer 399 400config MCUX_OS_TIMER 401 bool "MCUX OS Event timer" 402 depends on HAS_MCUX_OS_TIMER 403 default $(dt_compat_enabled,$(DT_COMPAT_NXP_OS_TIMER)) 404 select TICKLESS_CAPABLE 405 help 406 This module implements a kernel device driver for the NXP OS 407 event timer and provides the standard "system clock driver" interfaces. 408 409config MCUX_LPTMR_TIMER 410 bool "MCUX LPTMR timer" 411 depends on HAS_MCUX_LPTMR && !COUNTER_MCUX_LPTMR 412 help 413 This module implements a kernel device driver for the NXP MCUX Low 414 Power Timer (LPTMR) and provides the standard "system clock driver" 415 interfaces. 416 417endmenu 418
