1 /* 2 * Copyright (c) 2020 Espressif Systems (Shanghai) Co., Ltd. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef ZEPHYR_DRIVERS_SPI_ESP32_SPIM_H_ 8 #define ZEPHYR_DRIVERS_SPI_ESP32_SPIM_H_ 9 10 #define SPI_MASTER_FREQ_8M (APB_CLK_FREQ/10) 11 #define SPI_MASTER_FREQ_9M (APB_CLK_FREQ/9) /* 8.89MHz */ 12 #define SPI_MASTER_FREQ_10M (APB_CLK_FREQ/8) /* 10MHz */ 13 #define SPI_MASTER_FREQ_11M (APB_CLK_FREQ/7) /* 11.43MHz */ 14 #define SPI_MASTER_FREQ_13M (APB_CLK_FREQ/6) /* 13.33MHz */ 15 #define SPI_MASTER_FREQ_16M (APB_CLK_FREQ/5) /* 16MHz */ 16 #define SPI_MASTER_FREQ_20M (APB_CLK_FREQ/4) /* 20MHz */ 17 #define SPI_MASTER_FREQ_26M (APB_CLK_FREQ/3) /* 26.67MHz */ 18 #define SPI_MASTER_FREQ_40M (APB_CLK_FREQ/2) /* 40MHz */ 19 #define SPI_MASTER_FREQ_80M (APB_CLK_FREQ/1) /* 80MHz */ 20 21 struct spi_esp32_config { 22 spi_dev_t *spi; 23 const struct device *clock_dev; 24 int frequency; 25 int duty_cycle; 26 int input_delay_ns; 27 int irq_source; 28 29 clock_control_subsys_t clock_subsys; 30 31 struct { 32 int miso_s; 33 int mosi_s; 34 int sclk_s; 35 int csel_s; 36 } signals; 37 38 struct { 39 int miso; 40 int mosi; 41 int sclk; 42 int csel; 43 } pins; 44 }; 45 46 struct spi_esp32_data { 47 struct spi_context ctx; 48 spi_hal_context_t hal; 49 spi_hal_timing_conf_t timing_config; 50 spi_hal_dev_config_t dev_config; 51 spi_hal_trans_config_t trans_config; 52 uint8_t dfs; 53 int irq_line; 54 }; 55 56 #endif /* ZEPHYR_DRIVERS_SPI_ESP32_SPIM_H_ */ 57
