1 /* 2 * Copyright (c) 2018 Intel Corporation 3 * 4 * Author: Sathish Kuttan <sathish.k.kuttan@intel.com> 5 * 6 * SPDX-License-Identifier: Apache-2.0 7 */ 8 9 /** @file 10 * @brief Intel GNA device driver 11 * 12 * Device driver implementation for Intel's 13 * Gaussian Mixture Model and Neural Network Accelerator (GNA) 14 */ 15 16 #ifndef __INTEL_GNA__ 17 #define __INTEL_GNA__ 18 19 #ifdef __cplusplus 20 extern "C" { 21 #endif 22 23 /* number of requests that could be pending in driver */ 24 #define GNA_REQUEST_QUEUE_LEN CONFIG_INTEL_GNA_MAX_PENDING_REQUESTS 25 #define GNA_MAX_NUM_MODELS CONFIG_INTEL_GNA_MAX_MODELS 26 27 /* values must match config values in Kconfig.intel_gna */ 28 #define GNA_POWER_MODE_ALWAYS_ON 0 29 #define GNA_POWER_MODE_CLOCK_GATED 1 30 #define GNA_POWER_MODE_POWER_GATED 2 31 #define GNA_POWER_MODE_ALWAYS_OFF 3 32 33 #define INTEL_GNA_BASE_ADDR 0x0000E800 34 35 #define INTEL_GNA_IRQ_ID 0x00000506 36 #define INTEL_GNA_IRQ_PRIORITY 3 37 38 #define GNA_STS_INTR_PENDING BIT(31) 39 #define GNA_STS_SATURATION_OCCURRED BIT(17) 40 #define GNA_STS_BUFFER_FULL BIT(16) 41 #define GNA_STS_ERROR BIT(15) 42 #define GNA_STS_PARAM_OOR BIT(8) 43 #define GNA_STS_VIRT_ADDR_OOR BIT(7) 44 #define GNA_STS_STATS_VALID BIT(3) 45 #define GNA_STS_SUSP_PAUSE BIT(2) 46 #define GNA_STS_SUSP_BREAKP BIT(1) 47 #define GNA_STS_SCORE_COMPL BIT(0) 48 49 #define GNA_CTRL_INTR_DISABLE BIT(31) 50 #define GNA_CTRL_PM_IDLE_DISABLE BIT(18) 51 #define GNA_CTRL_PM_OVRIDE_CLK_ON BIT(17) 52 #define GNA_CTRL_PM_OVRIDE_PWR_ON BIT(16) 53 #define GNA_CTRL_STATS_ENABLE_STALL (1 << 12) 54 #define GNA_CTRL_STATS_MASK (BIT_MASK(4) << 12) 55 #define GNA_CTRL_ERR_INTR_ENABLE (1 << 10) 56 #define GNA_CTRL_COMPL_INTR_ENABLE (1 << 8) 57 #define GNA_CTRL_OPER_MODEL_XNN (1 << 5) 58 #define GNA_CTRL_ABORT_CLEAR (1 << 2) 59 #define GNA_CTRL_ACCEL_START (1 << 0) 60 #define GNA_CTRL_ACCEL_BUSY GNA_CTRL_ACCEL_START 61 62 #define GNA_CONFIG_DESC_PG_DIR_SIZE 64 63 64 #define GNA_LAYER_DESC_ALIGN (128) 65 66 #define GNA_ADDRESSABLE_MEM_SIZE L2_SRAM_SIZE 67 #define GNA_NUM_PG_TABLE_INDEX_BITS 10 68 #define GNA_NUM_PG_TABLE_ENTRIES BIT(GNA_NUM_PG_TABLE_INDEX_BITS) 69 #define GNA_PG_SIZE_IN_BITSHIFT 12 70 #define GNA_PG_SIZE_IN_BYTES BIT(GNA_PG_SIZE_IN_BITSHIFT) 71 72 #define GNA_SHIFT_RNDUP(value, shift) (((value) + BIT_MASK(shift)) >> (shift)) 73 74 #define GNA_NUM_PAGES(bytes) \ 75 GNA_SHIFT_RNDUP((bytes), GNA_PG_SIZE_IN_BITSHIFT) 76 77 #define GNA_PAGES_TO_BYTES(pages) ((pages) << GNA_PG_SIZE_IN_BITSHIFT) 78 79 #define GNA_MAX_NUM_PAGES GNA_NUM_PAGES(GNA_ADDRESSABLE_MEM_SIZE) 80 81 #define GNA_NUM_PG_TABLES_NEEDED \ 82 GNA_SHIFT_RNDUP(GNA_MAX_NUM_PAGES, GNA_NUM_PG_TABLE_INDEX_BITS) 83 84 #if GNA_NUM_PG_TABLES_NEEDED > GNA_CONFIG_DESC_PG_DIR_SIZE 85 #error GNA_NUM_PG_TABLES_NEEDED exceeds GNA_CONFIG_DESC_PG_DIR_SIZE 86 #endif 87 88 #define GNA_GET_BITS(val, b_hi, b_lo) ((((uint32_t)(val)) << (31 - (b_hi))) >> \ 89 (31 - (b_hi) + (b_lo))) 90 91 #define GNA_VA_PG_DIR(virt_addr) GNA_GET_BITS(virt_addr, 27, 22) 92 #define GNA_VA_PG_TABLE(virt_addr) GNA_GET_BITS(virt_addr, 21, 12) 93 94 #define GNA_PHYS_ADDR_TO_PAGE(addr) ((uint32_t)(addr) >> \ 95 GNA_PG_SIZE_IN_BITSHIFT) 96 #define GNA_PG_DIR_ENTRY(phys_addr) GNA_PHYS_ADDR_TO_PAGE(phys_addr) 97 #define GNA_PG_BASE(addr) ((uint32_t)(addr) & \ 98 ~BIT_MASK(GNA_PG_SIZE_IN_BITSHIFT)) 99 #define GNA_PG_OFFSET(addr) ((uint32_t)(addr) & \ 100 BIT_MASK(GNA_PG_SIZE_IN_BITSHIFT)) 101 #define GNA_PG_TABLE_ENTRY(phys_addr) GNA_PHYS_ADDR_TO_PAGE(phys_addr) 102 103 struct intel_gna_regs { 104 uint32_t gnasts; 105 uint32_t gnactrl; 106 uint32_t gnamctl; 107 uint32_t gnaptc; 108 uint32_t gnasc; 109 uint32_t gnaisi; 110 uint32_t gnais_low; 111 uint32_t gnais_high; 112 uint32_t gnabp_low; 113 uint32_t gnabp_high; 114 uint32_t reserved1[2]; 115 uint32_t gnadesbase; 116 uint32_t gnaibuffs; 117 uint32_t reserved2[2]; 118 uint32_t ovrcfgctl; 119 uint32_t reserved3[3]; 120 uint32_t gnaversion; 121 }; 122 123 struct intel_gna_config_desc { 124 uint32_t reserved1[64]; 125 uint32_t labase; /* layer array base */ 126 uint16_t lacnt; /* layer array count */ 127 uint16_t reserved2; 128 uint32_t reserved3[62]; 129 uint32_t vamaxaddr; /* virtual address max address */ 130 uint32_t reserved4[3]; 131 /* page directory entries */ 132 uint32_t pagedir[GNA_CONFIG_DESC_PG_DIR_SIZE]; 133 } __packed; 134 135 struct intel_gna_page_table { 136 uint32_t entry[GNA_NUM_PG_TABLE_ENTRIES]; 137 } __aligned(GNA_PG_SIZE_IN_BYTES); 138 139 struct intel_gna_layer_desc { 140 uint32_t gna_words[8]; 141 uint32_t inarrayptr; 142 uint32_t outarrayactptr; 143 uint32_t outarraysumptr; 144 uint32_t outfbarrayactptr; 145 uint32_t wtfltarrayptr; 146 uint32_t constarrayptr; 147 uint32_t actoutputslistptr; 148 uint32_t actfuncsectdefptr; 149 uint32_t reserved[16]; 150 } __packed __aligned(GNA_LAYER_DESC_ALIGN); 151 152 struct intel_gna_config { 153 struct gna_config config; 154 }; 155 156 struct intel_gna_model { 157 struct gna_model_info model; 158 void *input; 159 void *output; 160 void *vabase; 161 bool registered; 162 }; 163 164 struct intel_gna_pending_req { 165 struct intel_gna_model *model; 166 void *output; 167 size_t output_len; 168 gna_callback callback; 169 }; 170 171 struct intel_gna_pending_resp { 172 struct gna_inference_resp response; 173 gna_callback callback; 174 }; 175 176 enum gna_state { 177 GNA_STATE_UNINITIALIZED, 178 GNA_STATE_INITIALIZED, 179 GNA_STATE_IDLE, 180 GNA_STATE_ACTIVE, 181 }; 182 183 struct intel_gna_data { 184 /* 185 * gna_cb_work must be the first element in the structure 186 * since it will be typecast as intel_gna_data in the work handler 187 */ 188 struct k_work gna_work; 189 volatile struct intel_gna_regs *regs; 190 struct k_mem_slab model_slab; 191 struct intel_gna_model models[GNA_MAX_NUM_MODELS]; 192 struct k_msgq request_queue; 193 struct intel_gna_pending_req requests[GNA_REQUEST_QUEUE_LEN]; 194 struct k_msgq response_queue; 195 struct intel_gna_pending_resp responses[GNA_REQUEST_QUEUE_LEN]; 196 enum gna_state state; 197 198 struct gna_config config; 199 }; 200 201 #ifdef __cplusplus 202 } 203 #endif 204 205 #endif /* __INTEL_GNA__ */ 206
