1 /*
2 * Copyright (c) 2016 Open-RnD Sp. z o.o.
3 * Copyright (c) 2017 RnDity Sp. z o.o.
4 * Copyright (c) 2019 Linaro Limited
5 *
6 * SPDX-License-Identifier: Apache-2.0
7 */
8
9 /**
10 * @brief Driver for External interrupt/event controller in STM32 MCUs
11 *
12 * Driver is currently implemented to support following EXTI lines
13 * STM32F1/STM32F3: Lines 0 to 15. Lines > 15 not supported
14 * STM32F0/STM32L0/STM32L4/STM32L5/STM32G0/STM32G4: Lines 0 to 15.
15 * Lines > 15 are not mapped on an IRQ
16 * STM32F2/STM32F4: Lines 0 to 15, 16, 17 18, 21 and 22. Others not supported
17 * STM32F7: Lines 0 to 15, 16, 17 18, 21, 22 and 23. Others not supported
18 *
19 */
20
21 #define EXTI_NODE DT_INST(0, st_stm32_exti)
22
23 #include <device.h>
24 #include <soc.h>
25 #include <stm32_ll_exti.h>
26 #include <sys/__assert.h>
27 #include <drivers/interrupt_controller/exti_stm32.h>
28
29 #include "stm32_hsem.h"
30
31 #if defined(CONFIG_SOC_SERIES_STM32F0X) || \
32 defined(CONFIG_SOC_SERIES_STM32L0X) || \
33 defined(CONFIG_SOC_SERIES_STM32G0X)
34 const IRQn_Type exti_irq_table[] = {
35 EXTI0_1_IRQn, EXTI0_1_IRQn, EXTI2_3_IRQn, EXTI2_3_IRQn,
36 EXTI4_15_IRQn, EXTI4_15_IRQn, EXTI4_15_IRQn, EXTI4_15_IRQn,
37 EXTI4_15_IRQn, EXTI4_15_IRQn, EXTI4_15_IRQn, EXTI4_15_IRQn,
38 EXTI4_15_IRQn, EXTI4_15_IRQn, EXTI4_15_IRQn, EXTI4_15_IRQn
39 };
40 #elif defined(CONFIG_SOC_SERIES_STM32F1X) || \
41 defined(CONFIG_SOC_SERIES_STM32H7X) || \
42 defined(CONFIG_SOC_SERIES_STM32L1X) || \
43 defined(CONFIG_SOC_SERIES_STM32L4X) || \
44 defined(CONFIG_SOC_SERIES_STM32WBX) || \
45 defined(CONFIG_SOC_SERIES_STM32G4X) || \
46 defined(CONFIG_SOC_SERIES_STM32WLX)
47 const IRQn_Type exti_irq_table[] = {
48 EXTI0_IRQn, EXTI1_IRQn, EXTI2_IRQn, EXTI3_IRQn,
49 EXTI4_IRQn, EXTI9_5_IRQn, EXTI9_5_IRQn, EXTI9_5_IRQn,
50 EXTI9_5_IRQn, EXTI9_5_IRQn, EXTI15_10_IRQn, EXTI15_10_IRQn,
51 EXTI15_10_IRQn, EXTI15_10_IRQn, EXTI15_10_IRQn, EXTI15_10_IRQn
52 };
53 #elif defined(CONFIG_SOC_SERIES_STM32F3X)
54 const IRQn_Type exti_irq_table[] = {
55 EXTI0_IRQn, EXTI1_IRQn, EXTI2_TSC_IRQn, EXTI3_IRQn,
56 EXTI4_IRQn, EXTI9_5_IRQn, EXTI9_5_IRQn, EXTI9_5_IRQn,
57 EXTI9_5_IRQn, EXTI9_5_IRQn, EXTI15_10_IRQn, EXTI15_10_IRQn,
58 EXTI15_10_IRQn, EXTI15_10_IRQn, EXTI15_10_IRQn, EXTI15_10_IRQn
59 };
60 #elif defined(CONFIG_SOC_STM32F410RX) /* STM32F410RX has no OTG_FS_WKUP_IRQn */
61 const IRQn_Type exti_irq_table[] = {
62 EXTI0_IRQn, EXTI1_IRQn, EXTI2_IRQn, EXTI3_IRQn,
63 EXTI4_IRQn, EXTI9_5_IRQn, EXTI9_5_IRQn, EXTI9_5_IRQn,
64 EXTI9_5_IRQn, EXTI9_5_IRQn, EXTI15_10_IRQn, EXTI15_10_IRQn,
65 EXTI15_10_IRQn, EXTI15_10_IRQn, EXTI15_10_IRQn, EXTI15_10_IRQn,
66 PVD_IRQn, 0xFF, 0xFF, 0xFF,
67 0xFF, TAMP_STAMP_IRQn, RTC_WKUP_IRQn
68 };
69 #elif defined(CONFIG_SOC_SERIES_STM32F2X) || \
70 defined(CONFIG_SOC_SERIES_STM32F4X)
71 const IRQn_Type exti_irq_table[] = {
72 EXTI0_IRQn, EXTI1_IRQn, EXTI2_IRQn, EXTI3_IRQn,
73 EXTI4_IRQn, EXTI9_5_IRQn, EXTI9_5_IRQn, EXTI9_5_IRQn,
74 EXTI9_5_IRQn, EXTI9_5_IRQn, EXTI15_10_IRQn, EXTI15_10_IRQn,
75 EXTI15_10_IRQn, EXTI15_10_IRQn, EXTI15_10_IRQn, EXTI15_10_IRQn,
76 PVD_IRQn, 0xFF, OTG_FS_WKUP_IRQn, 0xFF,
77 0xFF, TAMP_STAMP_IRQn, RTC_WKUP_IRQn
78 };
79 #elif defined(CONFIG_SOC_SERIES_STM32F7X)
80 const IRQn_Type exti_irq_table[] = {
81 EXTI0_IRQn, EXTI1_IRQn, EXTI2_IRQn, EXTI3_IRQn,
82 EXTI4_IRQn, EXTI9_5_IRQn, EXTI9_5_IRQn, EXTI9_5_IRQn,
83 EXTI9_5_IRQn, EXTI9_5_IRQn, EXTI15_10_IRQn, EXTI15_10_IRQn,
84 EXTI15_10_IRQn, EXTI15_10_IRQn, EXTI15_10_IRQn, EXTI15_10_IRQn,
85 PVD_IRQn, 0xFF, OTG_FS_WKUP_IRQn, 0xFF,
86 0xFF, TAMP_STAMP_IRQn, RTC_WKUP_IRQn, LPTIM1_IRQn
87 };
88 #elif defined(CONFIG_SOC_SERIES_STM32MP1X) || \
89 defined(CONFIG_SOC_SERIES_STM32L5X) || \
90 defined(CONFIG_SOC_SERIES_STM32U5X)
91 const IRQn_Type exti_irq_table[] = {
92 EXTI0_IRQn, EXTI1_IRQn, EXTI2_IRQn, EXTI3_IRQn,
93 EXTI4_IRQn, EXTI5_IRQn, EXTI6_IRQn, EXTI7_IRQn,
94 EXTI8_IRQn, EXTI9_IRQn, EXTI10_IRQn, EXTI11_IRQn,
95 EXTI12_IRQn, EXTI13_IRQn, EXTI14_IRQn, EXTI15_IRQn
96 };
97 #endif
98
99 /* wrapper for user callback */
100 struct __exti_cb {
101 stm32_exti_callback_t cb;
102 void *data;
103 };
104
105 /* driver data */
106 struct stm32_exti_data {
107 /* per-line callbacks */
108 struct __exti_cb cb[ARRAY_SIZE(exti_irq_table)];
109 };
110
stm32_exti_enable(int line)111 void stm32_exti_enable(int line)
112 {
113 int irqnum = 0;
114
115 if (line >= ARRAY_SIZE(exti_irq_table)) {
116 __ASSERT_NO_MSG(line);
117 }
118
119 /* Get matching exti irq provided line thanks to irq_table */
120 irqnum = exti_irq_table[line];
121 if (irqnum == 0xFF) {
122 __ASSERT_NO_MSG(line);
123 }
124
125 /* Enable requested line interrupt */
126 #if defined(CONFIG_SOC_SERIES_STM32H7X) && defined(CONFIG_CPU_CORTEX_M4)
127 LL_C2_EXTI_EnableIT_0_31(1 << line);
128 #else
129 LL_EXTI_EnableIT_0_31(1 << line);
130 #endif
131
132 /* Enable exti irq interrupt */
133 irq_enable(irqnum);
134 }
135
stm32_exti_disable(int line)136 void stm32_exti_disable(int line)
137 {
138 z_stm32_hsem_lock(CFG_HW_EXTI_SEMID, HSEM_LOCK_DEFAULT_RETRY);
139
140 if (line < 32) {
141 #if defined(CONFIG_SOC_SERIES_STM32H7X) && defined(CONFIG_CPU_CORTEX_M4)
142 LL_C2_EXTI_DisableIT_0_31(1 << line);
143 #else
144 LL_EXTI_DisableIT_0_31(1 << line);
145 #endif
146 } else {
147 __ASSERT_NO_MSG(line);
148 }
149 z_stm32_hsem_unlock(CFG_HW_EXTI_SEMID);
150 }
151
152 /**
153 * @brief check if interrupt is pending
154 *
155 * @param line line number
156 */
stm32_exti_is_pending(int line)157 static inline int stm32_exti_is_pending(int line)
158 {
159 if (line < 32) {
160 #if defined(CONFIG_SOC_SERIES_STM32MP1X) || \
161 defined(CONFIG_SOC_SERIES_STM32G0X) || \
162 defined(CONFIG_SOC_SERIES_STM32L5X) || \
163 defined(CONFIG_SOC_SERIES_STM32U5X)
164 return (LL_EXTI_IsActiveRisingFlag_0_31(1 << line) ||
165 LL_EXTI_IsActiveFallingFlag_0_31(1 << line));
166 #elif defined(CONFIG_SOC_SERIES_STM32H7X) && defined(CONFIG_CPU_CORTEX_M4)
167 return LL_C2_EXTI_IsActiveFlag_0_31(1 << line);
168 #else
169 return LL_EXTI_IsActiveFlag_0_31(1 << line);
170 #endif
171 } else {
172 __ASSERT_NO_MSG(line);
173 return 0;
174 }
175 }
176
177 /**
178 * @brief clear pending interrupt bit
179 *
180 * @param line line number
181 */
stm32_exti_clear_pending(int line)182 static inline void stm32_exti_clear_pending(int line)
183 {
184 if (line < 32) {
185 #if defined(CONFIG_SOC_SERIES_STM32MP1X) || \
186 defined(CONFIG_SOC_SERIES_STM32G0X) || \
187 defined(CONFIG_SOC_SERIES_STM32L5X) || \
188 defined(CONFIG_SOC_SERIES_STM32U5X)
189 LL_EXTI_ClearRisingFlag_0_31(1 << line);
190 LL_EXTI_ClearFallingFlag_0_31(1 << line);
191 #elif defined(CONFIG_SOC_SERIES_STM32H7X) && defined(CONFIG_CPU_CORTEX_M4)
192 LL_C2_EXTI_ClearFlag_0_31(1 << line);
193 #else
194 LL_EXTI_ClearFlag_0_31(1 << line);
195 #endif
196 } else {
197 __ASSERT_NO_MSG(line);
198 }
199 }
200
stm32_exti_trigger(int line,int trigger)201 void stm32_exti_trigger(int line, int trigger)
202 {
203
204 if (line >= 32) {
205 __ASSERT_NO_MSG(line);
206 }
207
208 z_stm32_hsem_lock(CFG_HW_EXTI_SEMID, HSEM_LOCK_DEFAULT_RETRY);
209
210 switch (trigger) {
211 case STM32_EXTI_TRIG_NONE:
212 LL_EXTI_DisableRisingTrig_0_31(1 << line);
213 LL_EXTI_DisableFallingTrig_0_31(1 << line);
214 break;
215 case STM32_EXTI_TRIG_RISING:
216 LL_EXTI_EnableRisingTrig_0_31(1 << line);
217 LL_EXTI_DisableFallingTrig_0_31(1 << line);
218 break;
219 case STM32_EXTI_TRIG_FALLING:
220 LL_EXTI_EnableFallingTrig_0_31(1 << line);
221 LL_EXTI_DisableRisingTrig_0_31(1 << line);
222 break;
223 case STM32_EXTI_TRIG_BOTH:
224 LL_EXTI_EnableRisingTrig_0_31(1 << line);
225 LL_EXTI_EnableFallingTrig_0_31(1 << line);
226 break;
227 default:
228 __ASSERT_NO_MSG(trigger);
229 }
230 z_stm32_hsem_unlock(CFG_HW_EXTI_SEMID);
231 }
232
233 /**
234 * @brief EXTI ISR handler
235 *
236 * Check EXTI lines in range @min @max for pending interrupts
237 *
238 * @param arg isr argument
239 * @param min low end of EXTI# range
240 * @param max low end of EXTI# range
241 */
__stm32_exti_isr(int min,int max,const struct device * dev)242 static void __stm32_exti_isr(int min, int max, const struct device *dev)
243 {
244 struct stm32_exti_data *data = dev->data;
245 int line;
246
247 /* see which bits are set */
248 for (line = min; line < max; line++) {
249 /* check if interrupt is pending */
250 if (stm32_exti_is_pending(line)) {
251 /* clear pending interrupt */
252 stm32_exti_clear_pending(line);
253
254 /* run callback only if one is registered */
255 if (!data->cb[line].cb) {
256 continue;
257 }
258
259 data->cb[line].cb(line, data->cb[line].data);
260 }
261 }
262 }
263
264 #if defined(CONFIG_SOC_SERIES_STM32F0X) || \
265 defined(CONFIG_SOC_SERIES_STM32L0X) || \
266 defined(CONFIG_SOC_SERIES_STM32G0X)
__stm32_exti_isr_0_1(const void * arg)267 static inline void __stm32_exti_isr_0_1(const void *arg)
268 {
269 __stm32_exti_isr(0, 2, arg);
270 }
271
__stm32_exti_isr_2_3(const void * arg)272 static inline void __stm32_exti_isr_2_3(const void *arg)
273 {
274 __stm32_exti_isr(2, 4, arg);
275 }
276
__stm32_exti_isr_4_15(const void * arg)277 static inline void __stm32_exti_isr_4_15(const void *arg)
278 {
279 __stm32_exti_isr(4, 16, arg);
280 }
281
282 #else
__stm32_exti_isr_0(const void * arg)283 static inline void __stm32_exti_isr_0(const void *arg)
284 {
285 __stm32_exti_isr(0, 1, arg);
286 }
287
__stm32_exti_isr_1(const void * arg)288 static inline void __stm32_exti_isr_1(const void *arg)
289 {
290 __stm32_exti_isr(1, 2, arg);
291 }
292
__stm32_exti_isr_2(const void * arg)293 static inline void __stm32_exti_isr_2(const void *arg)
294 {
295 __stm32_exti_isr(2, 3, arg);
296 }
297
__stm32_exti_isr_3(const void * arg)298 static inline void __stm32_exti_isr_3(const void *arg)
299 {
300 __stm32_exti_isr(3, 4, arg);
301 }
302
__stm32_exti_isr_4(const void * arg)303 static inline void __stm32_exti_isr_4(const void *arg)
304 {
305 __stm32_exti_isr(4, 5, arg);
306 }
307
308 #if defined(CONFIG_SOC_SERIES_STM32MP1X) || \
309 defined(CONFIG_SOC_SERIES_STM32L5X) || \
310 defined(CONFIG_SOC_SERIES_STM32U5X)
__stm32_exti_isr_5(const void * arg)311 static inline void __stm32_exti_isr_5(const void *arg)
312 {
313 __stm32_exti_isr(5, 6, arg);
314 }
315
__stm32_exti_isr_6(const void * arg)316 static inline void __stm32_exti_isr_6(const void *arg)
317 {
318 __stm32_exti_isr(6, 7, arg);
319 }
320
__stm32_exti_isr_7(const void * arg)321 static inline void __stm32_exti_isr_7(const void *arg)
322 {
323 __stm32_exti_isr(7, 8, arg);
324 }
325
__stm32_exti_isr_8(const void * arg)326 static inline void __stm32_exti_isr_8(const void *arg)
327 {
328 __stm32_exti_isr(8, 9, arg);
329 }
330
__stm32_exti_isr_9(const void * arg)331 static inline void __stm32_exti_isr_9(const void *arg)
332 {
333 __stm32_exti_isr(9, 10, arg);
334 }
335
__stm32_exti_isr_10(const void * arg)336 static inline void __stm32_exti_isr_10(const void *arg)
337 {
338 __stm32_exti_isr(10, 11, arg);
339 }
340
__stm32_exti_isr_11(const void * arg)341 static inline void __stm32_exti_isr_11(const void *arg)
342 {
343 __stm32_exti_isr(11, 12, arg);
344 }
345
__stm32_exti_isr_12(const void * arg)346 static inline void __stm32_exti_isr_12(const void *arg)
347 {
348 __stm32_exti_isr(12, 13, arg);
349 }
350
__stm32_exti_isr_13(const void * arg)351 static inline void __stm32_exti_isr_13(const void *arg)
352 {
353 __stm32_exti_isr(13, 14, arg);
354 }
355
__stm32_exti_isr_14(const void * arg)356 static inline void __stm32_exti_isr_14(const void *arg)
357 {
358 __stm32_exti_isr(14, 15, arg);
359 }
360
__stm32_exti_isr_15(const void * arg)361 static inline void __stm32_exti_isr_15(const void *arg)
362 {
363 __stm32_exti_isr(15, 16, arg);
364 }
365 #endif
366
__stm32_exti_isr_9_5(const void * arg)367 static inline void __stm32_exti_isr_9_5(const void *arg)
368 {
369 __stm32_exti_isr(5, 10, arg);
370 }
371
__stm32_exti_isr_15_10(const void * arg)372 static inline void __stm32_exti_isr_15_10(const void *arg)
373 {
374 __stm32_exti_isr(10, 16, arg);
375 }
376
377 #if defined(CONFIG_SOC_SERIES_STM32F4X) || \
378 defined(CONFIG_SOC_SERIES_STM32F7X) || \
379 defined(CONFIG_SOC_SERIES_STM32F2X) || \
380 defined(CONFIG_SOC_SERIES_STM32MP1X)
__stm32_exti_isr_16(const void * arg)381 static inline void __stm32_exti_isr_16(const void *arg)
382 {
383 __stm32_exti_isr(16, 17, arg);
384 }
385
__stm32_exti_isr_18(const void * arg)386 static inline void __stm32_exti_isr_18(const void *arg)
387 {
388 __stm32_exti_isr(18, 19, arg);
389 }
390
__stm32_exti_isr_21(const void * arg)391 static inline void __stm32_exti_isr_21(const void *arg)
392 {
393 __stm32_exti_isr(21, 22, arg);
394 }
395
__stm32_exti_isr_22(const void * arg)396 static inline void __stm32_exti_isr_22(const void *arg)
397 {
398 __stm32_exti_isr(22, 23, arg);
399 }
400 #endif
401 #if defined(CONFIG_SOC_SERIES_STM32F7X) || \
402 defined(CONFIG_SOC_SERIES_STM32MP1X)
__stm32_exti_isr_23(const void * arg)403 static inline void __stm32_exti_isr_23(const void *arg)
404 {
405 __stm32_exti_isr(23, 24, arg);
406 }
407 #endif
408 #endif /* CONFIG_SOC_SERIES_STM32F0X */
409
410 static void __stm32_exti_connect_irqs(const struct device *dev);
411
412 /**
413 * @brief initialize EXTI device driver
414 */
stm32_exti_init(const struct device * dev)415 static int stm32_exti_init(const struct device *dev)
416 {
417 __stm32_exti_connect_irqs(dev);
418
419 return 0;
420 }
421
422 static struct stm32_exti_data exti_data;
423 DEVICE_DT_DEFINE(EXTI_NODE, &stm32_exti_init,
424 NULL,
425 &exti_data, NULL,
426 PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
427 NULL);
428
429 /**
430 * @brief set & unset for the interrupt callbacks
431 */
stm32_exti_set_callback(int line,stm32_exti_callback_t cb,void * arg)432 int stm32_exti_set_callback(int line, stm32_exti_callback_t cb, void *arg)
433 {
434 const struct device *dev = DEVICE_DT_GET(EXTI_NODE);
435 struct stm32_exti_data *data = dev->data;
436
437 if (data->cb[line].cb) {
438 return -EBUSY;
439 }
440
441 data->cb[line].cb = cb;
442 data->cb[line].data = arg;
443
444 return 0;
445 }
446
stm32_exti_unset_callback(int line)447 void stm32_exti_unset_callback(int line)
448 {
449 const struct device *dev = DEVICE_DT_GET(EXTI_NODE);
450 struct stm32_exti_data *data = dev->data;
451
452 data->cb[line].cb = NULL;
453 data->cb[line].data = NULL;
454 }
455
456 /**
457 * @brief connect all interrupts
458 */
__stm32_exti_connect_irqs(const struct device * dev)459 static void __stm32_exti_connect_irqs(const struct device *dev)
460 {
461 ARG_UNUSED(dev);
462
463 #if defined(CONFIG_SOC_SERIES_STM32F0X) || \
464 defined(CONFIG_SOC_SERIES_STM32L0X) || \
465 defined(CONFIG_SOC_SERIES_STM32G0X)
466 IRQ_CONNECT(EXTI0_1_IRQn,
467 CONFIG_EXTI_STM32_EXTI1_0_IRQ_PRI,
468 __stm32_exti_isr_0_1, DEVICE_DT_GET(EXTI_NODE),
469 0);
470 IRQ_CONNECT(EXTI2_3_IRQn,
471 CONFIG_EXTI_STM32_EXTI3_2_IRQ_PRI,
472 __stm32_exti_isr_2_3, DEVICE_DT_GET(EXTI_NODE),
473 0);
474 IRQ_CONNECT(EXTI4_15_IRQn,
475 CONFIG_EXTI_STM32_EXTI15_4_IRQ_PRI,
476 __stm32_exti_isr_4_15, DEVICE_DT_GET(EXTI_NODE),
477 0);
478 #elif defined(CONFIG_SOC_SERIES_STM32F1X) || \
479 defined(CONFIG_SOC_SERIES_STM32F2X) || \
480 defined(CONFIG_SOC_SERIES_STM32F3X) || \
481 defined(CONFIG_SOC_SERIES_STM32F4X) || \
482 defined(CONFIG_SOC_SERIES_STM32F7X) || \
483 defined(CONFIG_SOC_SERIES_STM32H7X) || \
484 defined(CONFIG_SOC_SERIES_STM32L1X) || \
485 defined(CONFIG_SOC_SERIES_STM32L4X) || \
486 defined(CONFIG_SOC_SERIES_STM32L5X) || \
487 defined(CONFIG_SOC_SERIES_STM32MP1X) || \
488 defined(CONFIG_SOC_SERIES_STM32U5X) || \
489 defined(CONFIG_SOC_SERIES_STM32WBX) || \
490 defined(CONFIG_SOC_SERIES_STM32G4X) || \
491 defined(CONFIG_SOC_SERIES_STM32WLX)
492 IRQ_CONNECT(EXTI0_IRQn,
493 CONFIG_EXTI_STM32_EXTI0_IRQ_PRI,
494 __stm32_exti_isr_0, DEVICE_DT_GET(EXTI_NODE),
495 0);
496 IRQ_CONNECT(EXTI1_IRQn,
497 CONFIG_EXTI_STM32_EXTI1_IRQ_PRI,
498 __stm32_exti_isr_1, DEVICE_DT_GET(EXTI_NODE),
499 0);
500 #ifdef CONFIG_SOC_SERIES_STM32F3X
501 IRQ_CONNECT(EXTI2_TSC_IRQn,
502 CONFIG_EXTI_STM32_EXTI2_IRQ_PRI,
503 __stm32_exti_isr_2, DEVICE_DT_GET(EXTI_NODE),
504 0);
505 #else
506 IRQ_CONNECT(EXTI2_IRQn,
507 CONFIG_EXTI_STM32_EXTI2_IRQ_PRI,
508 __stm32_exti_isr_2, DEVICE_DT_GET(EXTI_NODE),
509 0);
510 #endif /* CONFIG_SOC_SERIES_STM32F3X */
511 IRQ_CONNECT(EXTI3_IRQn,
512 CONFIG_EXTI_STM32_EXTI3_IRQ_PRI,
513 __stm32_exti_isr_3, DEVICE_DT_GET(EXTI_NODE),
514 0);
515 IRQ_CONNECT(EXTI4_IRQn,
516 CONFIG_EXTI_STM32_EXTI4_IRQ_PRI,
517 __stm32_exti_isr_4, DEVICE_DT_GET(EXTI_NODE),
518 0);
519 #if !defined(CONFIG_SOC_SERIES_STM32MP1X) && \
520 !defined(CONFIG_SOC_SERIES_STM32L5X) && \
521 !defined(CONFIG_SOC_SERIES_STM32U5X)
522 IRQ_CONNECT(EXTI9_5_IRQn,
523 CONFIG_EXTI_STM32_EXTI9_5_IRQ_PRI,
524 __stm32_exti_isr_9_5, DEVICE_DT_GET(EXTI_NODE),
525 0);
526 IRQ_CONNECT(EXTI15_10_IRQn,
527 CONFIG_EXTI_STM32_EXTI15_10_IRQ_PRI,
528 __stm32_exti_isr_15_10, DEVICE_DT_GET(EXTI_NODE),
529 0);
530 #else
531 IRQ_CONNECT(EXTI5_IRQn,
532 CONFIG_EXTI_STM32_EXTI5_IRQ_PRI,
533 __stm32_exti_isr_5, DEVICE_DT_GET(EXTI_NODE),
534 0);
535 IRQ_CONNECT(EXTI6_IRQn,
536 CONFIG_EXTI_STM32_EXTI6_IRQ_PRI,
537 __stm32_exti_isr_6, DEVICE_DT_GET(EXTI_NODE),
538 0);
539 IRQ_CONNECT(EXTI7_IRQn,
540 CONFIG_EXTI_STM32_EXTI7_IRQ_PRI,
541 __stm32_exti_isr_7, DEVICE_DT_GET(EXTI_NODE),
542 0);
543 IRQ_CONNECT(EXTI8_IRQn,
544 CONFIG_EXTI_STM32_EXTI8_IRQ_PRI,
545 __stm32_exti_isr_8, DEVICE_DT_GET(EXTI_NODE),
546 0);
547 IRQ_CONNECT(EXTI9_IRQn,
548 CONFIG_EXTI_STM32_EXTI9_IRQ_PRI,
549 __stm32_exti_isr_9, DEVICE_DT_GET(EXTI_NODE),
550 0);
551 IRQ_CONNECT(EXTI10_IRQn,
552 CONFIG_EXTI_STM32_EXTI10_IRQ_PRI,
553 __stm32_exti_isr_10, DEVICE_DT_GET(EXTI_NODE),
554 0);
555 IRQ_CONNECT(EXTI11_IRQn,
556 CONFIG_EXTI_STM32_EXTI11_IRQ_PRI,
557 __stm32_exti_isr_11, DEVICE_DT_GET(EXTI_NODE),
558 0);
559 IRQ_CONNECT(EXTI12_IRQn,
560 CONFIG_EXTI_STM32_EXTI12_IRQ_PRI,
561 __stm32_exti_isr_12, DEVICE_DT_GET(EXTI_NODE),
562 0);
563 IRQ_CONNECT(EXTI13_IRQn,
564 CONFIG_EXTI_STM32_EXTI13_IRQ_PRI,
565 __stm32_exti_isr_13, DEVICE_DT_GET(EXTI_NODE),
566 0);
567 IRQ_CONNECT(EXTI14_IRQn,
568 CONFIG_EXTI_STM32_EXTI14_IRQ_PRI,
569 __stm32_exti_isr_14, DEVICE_DT_GET(EXTI_NODE),
570 0);
571 IRQ_CONNECT(EXTI15_IRQn,
572 CONFIG_EXTI_STM32_EXTI15_IRQ_PRI,
573 __stm32_exti_isr_15, DEVICE_DT_GET(EXTI_NODE),
574 0);
575 #endif /* CONFIG_SOC_SERIES_STM32MP1X || CONFIG_SOC_SERIES_STM32L5X */
576
577 #if defined(CONFIG_SOC_SERIES_STM32F2X) || \
578 defined(CONFIG_SOC_SERIES_STM32F4X) || \
579 defined(CONFIG_SOC_SERIES_STM32F7X)
580 IRQ_CONNECT(PVD_IRQn,
581 CONFIG_EXTI_STM32_PVD_IRQ_PRI,
582 __stm32_exti_isr_16, DEVICE_DT_GET(EXTI_NODE),
583 0);
584 #if !defined(CONFIG_SOC_STM32F410RX)
585 IRQ_CONNECT(OTG_FS_WKUP_IRQn,
586 CONFIG_EXTI_STM32_OTG_FS_WKUP_IRQ_PRI,
587 __stm32_exti_isr_18, DEVICE_DT_GET(EXTI_NODE),
588 0);
589 #endif
590 IRQ_CONNECT(TAMP_STAMP_IRQn,
591 CONFIG_EXTI_STM32_TAMP_STAMP_IRQ_PRI,
592 __stm32_exti_isr_21, DEVICE_DT_GET(EXTI_NODE),
593 0);
594 IRQ_CONNECT(RTC_WKUP_IRQn,
595 CONFIG_EXTI_STM32_RTC_WKUP_IRQ_PRI,
596 __stm32_exti_isr_22, DEVICE_DT_GET(EXTI_NODE),
597 0);
598 #endif
599 #if CONFIG_SOC_SERIES_STM32F7X
600 IRQ_CONNECT(LPTIM1_IRQn,
601 CONFIG_EXTI_STM32_LPTIM1_IRQ_PRI,
602 __stm32_exti_isr_23, DEVICE_DT_GET(EXTI_NODE),
603 0);
604 #endif /* CONFIG_SOC_SERIES_STM32F7X */
605 #endif
606 }
607
