1 /* 2 * Copyright (c) 2017 PHYTEC Messtechnik GmbH 3 * 4 * Portions of this file are derived from ieee802154_cc2520.h that is 5 * Copyright (c) 2016 Intel Corporation. 6 * 7 * SPDX-License-Identifier: Apache-2.0 8 */ 9 10 #ifndef ZEPHYR_DRIVERS_IEEE802154_IEEE802154_MCR20A_H_ 11 #define ZEPHYR_DRIVERS_IEEE802154_IEEE802154_MCR20A_H_ 12 13 #include <linker/sections.h> 14 #include <sys/atomic.h> 15 #include <drivers/spi.h> 16 17 /* Runtime context structure 18 *************************** 19 */ 20 struct mcr20a_context { 21 struct net_if *iface; 22 /**************************/ 23 const struct device *irq_gpio; 24 const struct device *reset_gpio; 25 struct gpio_callback irqb_cb; 26 const struct device *spi; 27 struct spi_config spi_cfg; 28 #if DT_INST_SPI_DEV_HAS_CS_GPIOS(0) 29 struct spi_cs_control cs_ctrl; 30 #endif 31 uint8_t mac_addr[8]; 32 struct k_mutex phy_mutex; 33 struct k_sem isr_sem; 34 /*********TX + CCA*********/ 35 struct k_sem seq_sync; 36 atomic_t seq_retval; 37 /************RX************/ 38 K_KERNEL_STACK_MEMBER(mcr20a_rx_stack, 39 CONFIG_IEEE802154_MCR20A_RX_STACK_SIZE); 40 struct k_thread mcr20a_rx_thread; 41 }; 42 43 #include "ieee802154_mcr20a_regs.h" 44 45 uint8_t z_mcr20a_read_reg(struct mcr20a_context *dev, bool dreg, uint8_t addr); 46 bool z_mcr20a_write_reg(struct mcr20a_context *dev, bool dreg, uint8_t addr, 47 uint8_t value); 48 bool z_mcr20a_write_burst(struct mcr20a_context *dev, bool dreg, uint16_t addr, 49 uint8_t *data_buf, uint8_t len); 50 bool z_mcr20a_read_burst(struct mcr20a_context *dev, bool dreg, uint16_t addr, 51 uint8_t *data_buf, uint8_t len); 52 53 #define DEFINE_REG_READ(__reg_name, __reg_addr, __dreg) \ 54 static inline uint8_t read_reg_##__reg_name(struct mcr20a_context *dev) \ 55 { \ 56 return z_mcr20a_read_reg(dev, __dreg, __reg_addr); \ 57 } 58 59 #define DEFINE_REG_WRITE(__reg_name, __reg_addr, __dreg) \ 60 static inline bool write_reg_##__reg_name(struct mcr20a_context *dev, \ 61 uint8_t value) \ 62 { \ 63 return z_mcr20a_write_reg(dev, __dreg, __reg_addr, value); \ 64 } 65 66 #define DEFINE_DREG_READ(__reg_name, __reg_addr) \ 67 DEFINE_REG_READ(__reg_name, __reg_addr, true) 68 #define DEFINE_DREG_WRITE(__reg_name, __reg_addr) \ 69 DEFINE_REG_WRITE(__reg_name, __reg_addr, true) 70 71 #define DEFINE_IREG_READ(__reg_name, __reg_addr) \ 72 DEFINE_REG_READ(__reg_name, __reg_addr, false) 73 #define DEFINE_IREG_WRITE(__reg_name, __reg_addr) \ 74 DEFINE_REG_WRITE(__reg_name, __reg_addr, false) 75 76 DEFINE_DREG_READ(irqsts1, MCR20A_IRQSTS1) 77 DEFINE_DREG_READ(irqsts2, MCR20A_IRQSTS2) 78 DEFINE_DREG_READ(irqsts3, MCR20A_IRQSTS3) 79 DEFINE_DREG_READ(phy_ctrl1, MCR20A_PHY_CTRL1) 80 DEFINE_DREG_READ(phy_ctrl2, MCR20A_PHY_CTRL2) 81 DEFINE_DREG_READ(phy_ctrl3, MCR20A_PHY_CTRL3) 82 DEFINE_DREG_READ(rx_frm_len, MCR20A_RX_FRM_LEN) 83 DEFINE_DREG_READ(phy_ctrl4, MCR20A_PHY_CTRL4) 84 DEFINE_DREG_READ(src_ctrl, MCR20A_SRC_CTRL) 85 DEFINE_DREG_READ(cca1_ed_fnl, MCR20A_CCA1_ED_FNL) 86 DEFINE_DREG_READ(pll_int0, MCR20A_PLL_INT0) 87 DEFINE_DREG_READ(pa_pwr, MCR20A_PA_PWR) 88 DEFINE_DREG_READ(seq_state, MCR20A_SEQ_STATE) 89 DEFINE_DREG_READ(lqi_value, MCR20A_LQI_VALUE) 90 DEFINE_DREG_READ(rssi_cca_cnt, MCR20A_RSSI_CCA_CNT) 91 DEFINE_DREG_READ(asm_ctrl1, MCR20A_ASM_CTRL1) 92 DEFINE_DREG_READ(asm_ctrl2, MCR20A_ASM_CTRL2) 93 DEFINE_DREG_READ(overwrite_ver, MCR20A_OVERWRITE_VER) 94 DEFINE_DREG_READ(clk_out_ctrl, MCR20A_CLK_OUT_CTRL) 95 DEFINE_DREG_READ(pwr_modes, MCR20A_PWR_MODES) 96 97 DEFINE_DREG_WRITE(irqsts1, MCR20A_IRQSTS1) 98 DEFINE_DREG_WRITE(irqsts2, MCR20A_IRQSTS2) 99 DEFINE_DREG_WRITE(irqsts3, MCR20A_IRQSTS3) 100 DEFINE_DREG_WRITE(phy_ctrl1, MCR20A_PHY_CTRL1) 101 DEFINE_DREG_WRITE(phy_ctrl2, MCR20A_PHY_CTRL2) 102 DEFINE_DREG_WRITE(phy_ctrl3, MCR20A_PHY_CTRL3) 103 DEFINE_DREG_WRITE(phy_ctrl4, MCR20A_PHY_CTRL4) 104 DEFINE_DREG_WRITE(src_ctrl, MCR20A_SRC_CTRL) 105 DEFINE_DREG_WRITE(pll_int0, MCR20A_PLL_INT0) 106 DEFINE_DREG_WRITE(pa_pwr, MCR20A_PA_PWR) 107 DEFINE_DREG_WRITE(asm_ctrl1, MCR20A_ASM_CTRL1) 108 DEFINE_DREG_WRITE(asm_ctrl2, MCR20A_ASM_CTRL2) 109 DEFINE_DREG_WRITE(overwrite_ver, MCR20A_OVERWRITE_VER) 110 DEFINE_DREG_WRITE(clk_out_ctrl, MCR20A_CLK_OUT_CTRL) 111 DEFINE_DREG_WRITE(pwr_modes, MCR20A_PWR_MODES) 112 113 DEFINE_IREG_READ(part_id, MCR20A_PART_ID) 114 DEFINE_IREG_READ(rx_frame_filter, MCR20A_RX_FRAME_FILTER) 115 DEFINE_IREG_READ(cca1_thresh, MCR20A_CCA1_THRESH) 116 DEFINE_IREG_READ(cca1_ed_offset_comp, MCR20A_CCA1_ED_OFFSET_COMP) 117 DEFINE_IREG_READ(lqi_offset_comp, MCR20A_LQI_OFFSET_COMP) 118 DEFINE_IREG_READ(cca_ctrl, MCR20A_CCA_CTRL) 119 DEFINE_IREG_READ(cca2_corr_peaks, MCR20A_CCA2_CORR_PEAKS) 120 DEFINE_IREG_READ(cca2_thresh, MCR20A_CCA2_THRESH) 121 DEFINE_IREG_READ(tmr_prescale, MCR20A_TMR_PRESCALE) 122 DEFINE_IREG_READ(rx_byte_count, MCR20A_RX_BYTE_COUNT) 123 DEFINE_IREG_READ(rx_wtr_mark, MCR20A_RX_WTR_MARK) 124 125 DEFINE_IREG_WRITE(part_id, MCR20A_PART_ID) 126 DEFINE_IREG_WRITE(rx_frame_filter, MCR20A_RX_FRAME_FILTER) 127 DEFINE_IREG_WRITE(cca1_thresh, MCR20A_CCA1_THRESH) 128 DEFINE_IREG_WRITE(cca1_ed_offset_comp, MCR20A_CCA1_ED_OFFSET_COMP) 129 DEFINE_IREG_WRITE(lqi_offset_comp, MCR20A_LQI_OFFSET_COMP) 130 DEFINE_IREG_WRITE(cca_ctrl, MCR20A_CCA_CTRL) 131 DEFINE_IREG_WRITE(cca2_corr_peaks, MCR20A_CCA2_CORR_PEAKS) 132 DEFINE_IREG_WRITE(cca2_thresh, MCR20A_CCA2_THRESH) 133 DEFINE_IREG_WRITE(tmr_prescale, MCR20A_TMR_PRESCALE) 134 DEFINE_IREG_WRITE(rx_byte_count, MCR20A_RX_BYTE_COUNT) 135 DEFINE_IREG_WRITE(rx_wtr_mark, MCR20A_RX_WTR_MARK) 136 137 #define DEFINE_BITS_SET(__reg_name, __reg_addr, __nibble) \ 138 static inline uint8_t set_bits_##__reg_name(uint8_t value) \ 139 { \ 140 value = (value << __reg_addr##__nibble##_SHIFT) & \ 141 __reg_addr##__nibble##_MASK; \ 142 return value; \ 143 } 144 145 DEFINE_BITS_SET(phy_ctrl1_xcvseq, MCR20A_PHY_CTRL1, _XCVSEQ) 146 DEFINE_BITS_SET(phy_ctrl4_ccatype, MCR20A_PHY_CTRL4, _CCATYPE) 147 DEFINE_BITS_SET(pll_int0_val, MCR20A_PLL_INT0, _VAL) 148 DEFINE_BITS_SET(pa_pwr_val, MCR20A_PA_PWR, _VAL) 149 DEFINE_BITS_SET(tmr_prescale, MCR20A_TMR_PRESCALE, _VAL) 150 DEFINE_BITS_SET(clk_out_div, MCR20A_CLK_OUT, _DIV) 151 152 #define DEFINE_BURST_WRITE(__reg_addr, __addr, __sz, __dreg) \ 153 static inline bool write_burst_##__reg_addr( \ 154 struct mcr20a_context *dev, uint8_t *buf) \ 155 { \ 156 return z_mcr20a_write_burst(dev, __dreg, __addr, buf, __sz); \ 157 } 158 159 #define DEFINE_BURST_READ(__reg_addr, __addr, __sz, __dreg) \ 160 static inline bool read_burst_##__reg_addr(struct mcr20a_context *dev, \ 161 uint8_t *buf) \ 162 { \ 163 return z_mcr20a_read_burst(dev, __dreg, __addr, buf, __sz); \ 164 } 165 166 DEFINE_BURST_WRITE(t1cmp, MCR20A_T1CMP_LSB, 3, true) 167 DEFINE_BURST_WRITE(t2cmp, MCR20A_T2CMP_LSB, 3, true) 168 DEFINE_BURST_WRITE(t3cmp, MCR20A_T3CMP_LSB, 3, true) 169 DEFINE_BURST_WRITE(t4cmp, MCR20A_T4CMP_LSB, 3, true) 170 DEFINE_BURST_WRITE(t2primecmp, MCR20A_T2PRIMECMP_LSB, 2, true) 171 DEFINE_BURST_WRITE(pll_int0, MCR20A_PLL_INT0, 3, true) 172 DEFINE_BURST_WRITE(irqsts1_irqsts3, MCR20A_IRQSTS1, 3, true) 173 DEFINE_BURST_WRITE(irqsts1_ctrl1, MCR20A_IRQSTS1, 4, true) 174 175 DEFINE_BURST_WRITE(pan_id, MCR20A_MACPANID0_LSB, 2, false) 176 DEFINE_BURST_WRITE(short_addr, MCR20A_MACSHORTADDRS0_LSB, 2, false) 177 DEFINE_BURST_WRITE(ext_addr, MCR20A_MACLONGADDRS0_0, 8, false) 178 179 DEFINE_BURST_READ(event_timer, MCR20A_EVENT_TIMER_LSB, 3, true) 180 DEFINE_BURST_READ(irqsts1_ctrl4, MCR20A_IRQSTS1, 8, true) 181 182 #endif /* ZEPHYR_DRIVERS_IEEE802154_IEEE802154_MCR20A_H_ */ 183
