1 /*
2 * Copyright (c) 2020 Henrik Brix Andersen <henrik@brixandersen.dk>
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT xlnx_xps_gpio_1_00_a
8
9 #include <device.h>
10 #include <drivers/gpio.h>
11 #include <sys/sys_io.h>
12
13 #include "gpio_utils.h"
14
15 /* AXI GPIO v2 register offsetd (See Xilinx PG144 for details) */
16 #define GPIO_DATA_OFFSET 0x0000
17 #define GPIO_TRI_OFFSET 0x0004
18 #define GPIO2_DATA_OFFSET 0x0008
19 #define GPIO2_TRI_OFFSET 0x000c
20 #define GIER_OFFSET 0x011c
21 #define IPISR_OFFSET 0x0120
22 #define IPIER_OFFSET 0x0128
23
24 /* GIER bit definitions */
25 #define GIER_GIE BIT(31)
26
27 /* IPISR and IPIER bit definitions */
28 #define IPIXX_CH1_IE BIT(0)
29 #define IPIXX_CH2_IE BIT(1)
30
31 /* Maximum number of GPIOs supported per channel */
32 #define MAX_GPIOS 32
33
34 struct gpio_xlnx_axi_config {
35 /* gpio_driver_config needs to be first */
36 struct gpio_driver_config common;
37 mm_reg_t base;
38 bool all_inputs : 1;
39 bool all_outputs : 1;
40 };
41
42 struct gpio_xlnx_axi_data {
43 /* gpio_driver_data needs to be first */
44 struct gpio_driver_data common;
45 /* Shadow registers for data out and tristate */
46 uint32_t dout;
47 uint32_t tri;
48 };
49
gpio_xlnx_axi_read_data(const struct device * dev)50 static inline uint32_t gpio_xlnx_axi_read_data(const struct device *dev)
51 {
52 const struct gpio_xlnx_axi_config *config = dev->config;
53
54 return sys_read32(config->base + GPIO_DATA_OFFSET);
55 }
56
gpio_xlnx_axi_write_data(const struct device * dev,uint32_t val)57 static inline void gpio_xlnx_axi_write_data(const struct device *dev,
58 uint32_t val)
59 {
60 const struct gpio_xlnx_axi_config *config = dev->config;
61
62 sys_write32(val, config->base + GPIO_DATA_OFFSET);
63 }
64
gpio_xlnx_axi_write_tri(const struct device * dev,uint32_t val)65 static inline void gpio_xlnx_axi_write_tri(const struct device *dev,
66 uint32_t val)
67 {
68 const struct gpio_xlnx_axi_config *config = dev->config;
69
70 sys_write32(val, config->base + GPIO_TRI_OFFSET);
71 }
72
gpio_xlnx_axi_pin_configure(const struct device * dev,gpio_pin_t pin,gpio_flags_t flags)73 static int gpio_xlnx_axi_pin_configure(const struct device *dev,
74 gpio_pin_t pin,
75 gpio_flags_t flags)
76 {
77 const struct gpio_xlnx_axi_config *config = dev->config;
78 struct gpio_xlnx_axi_data *data = dev->data;
79 unsigned int key;
80
81 if (!(BIT(pin) & config->common.port_pin_mask)) {
82 return -EINVAL;
83 }
84
85 if (((flags & GPIO_INPUT) != 0) && ((flags & GPIO_OUTPUT) != 0)) {
86 return -ENOTSUP;
87 }
88
89 if ((flags & GPIO_SINGLE_ENDED) != 0) {
90 return -ENOTSUP;
91 }
92
93 if ((flags & (GPIO_PULL_UP | GPIO_PULL_DOWN)) != 0) {
94 return -ENOTSUP;
95 }
96
97 if (((flags & GPIO_INPUT) != 0) && config->all_outputs) {
98 return -ENOTSUP;
99 }
100
101 if (((flags & GPIO_OUTPUT) != 0) && config->all_inputs) {
102 return -ENOTSUP;
103 }
104
105 key = irq_lock();
106
107 switch (flags & GPIO_DIR_MASK) {
108 case GPIO_INPUT:
109 data->tri |= BIT(pin);
110 break;
111 case GPIO_OUTPUT:
112 if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0) {
113 data->dout |= BIT(pin);
114 } else if ((flags & GPIO_OUTPUT_INIT_LOW) != 0) {
115 data->dout &= ~BIT(pin);
116 }
117 data->tri &= ~BIT(pin);
118 break;
119 default:
120 return -ENOTSUP;
121 }
122
123 gpio_xlnx_axi_write_data(dev, data->dout);
124 gpio_xlnx_axi_write_tri(dev, data->tri);
125
126 irq_unlock(key);
127
128 return 0;
129 }
130
gpio_xlnx_axi_port_get_raw(const struct device * dev,gpio_port_value_t * value)131 static int gpio_xlnx_axi_port_get_raw(const struct device *dev,
132 gpio_port_value_t *value)
133 {
134 *value = gpio_xlnx_axi_read_data(dev);
135 return 0;
136 }
137
gpio_xlnx_axi_port_set_masked_raw(const struct device * dev,gpio_port_pins_t mask,gpio_port_value_t value)138 static int gpio_xlnx_axi_port_set_masked_raw(const struct device *dev,
139 gpio_port_pins_t mask,
140 gpio_port_value_t value)
141 {
142 struct gpio_xlnx_axi_data *data = dev->data;
143 unsigned int key;
144
145 key = irq_lock();
146 data->dout = (data->dout & ~mask) | (mask & value);
147 gpio_xlnx_axi_write_data(dev, data->dout);
148 irq_unlock(key);
149
150 return 0;
151 }
152
gpio_xlnx_axi_port_set_bits_raw(const struct device * dev,gpio_port_pins_t pins)153 static int gpio_xlnx_axi_port_set_bits_raw(const struct device *dev,
154 gpio_port_pins_t pins)
155 {
156 struct gpio_xlnx_axi_data *data = dev->data;
157 unsigned int key;
158
159 key = irq_lock();
160 data->dout |= pins;
161 gpio_xlnx_axi_write_data(dev, data->dout);
162 irq_unlock(key);
163
164 return 0;
165 }
166
gpio_xlnx_axi_port_clear_bits_raw(const struct device * dev,gpio_port_pins_t pins)167 static int gpio_xlnx_axi_port_clear_bits_raw(const struct device *dev,
168 gpio_port_pins_t pins)
169 {
170 struct gpio_xlnx_axi_data *data = dev->data;
171 unsigned int key;
172
173 key = irq_lock();
174 data->dout &= ~pins;
175 gpio_xlnx_axi_write_data(dev, data->dout);
176 irq_unlock(key);
177
178 return 0;
179 }
180
gpio_xlnx_axi_port_toggle_bits(const struct device * dev,gpio_port_pins_t pins)181 static int gpio_xlnx_axi_port_toggle_bits(const struct device *dev,
182 gpio_port_pins_t pins)
183 {
184 struct gpio_xlnx_axi_data *data = dev->data;
185 unsigned int key;
186
187 key = irq_lock();
188 data->dout ^= pins;
189 gpio_xlnx_axi_write_data(dev, data->dout);
190 irq_unlock(key);
191
192 return 0;
193 }
194
gpio_xlnx_axi_pin_interrupt_configure(const struct device * dev,gpio_pin_t pin,enum gpio_int_mode mode,enum gpio_int_trig trig)195 static int gpio_xlnx_axi_pin_interrupt_configure(const struct device *dev,
196 gpio_pin_t pin,
197 enum gpio_int_mode mode,
198 enum gpio_int_trig trig)
199 {
200 ARG_UNUSED(dev);
201 ARG_UNUSED(pin);
202 ARG_UNUSED(mode);
203 ARG_UNUSED(trig);
204
205 /*
206 * The Xilinx AXI GPIO IP only supports a port-wide pin change
207 * interrupt. This does not map well to the current Zephyr GPIO IRQ API.
208 */
209 return -ENOTSUP;
210 }
211
gpio_xlnx_axi_manage_callback(const struct device * dev,struct gpio_callback * cb,bool set)212 static int gpio_xlnx_axi_manage_callback(const struct device *dev,
213 struct gpio_callback *cb,
214 bool set)
215 {
216 ARG_UNUSED(dev);
217 ARG_UNUSED(cb);
218 ARG_UNUSED(set);
219
220 return -ENOTSUP;
221 }
222
gpio_xlnx_axi_get_pending_int(const struct device * dev)223 static uint32_t gpio_xlnx_axi_get_pending_int(const struct device *dev)
224 {
225 return 0;
226 }
227
gpio_xlnx_axi_init(const struct device * dev)228 static int gpio_xlnx_axi_init(const struct device *dev)
229 {
230 struct gpio_xlnx_axi_data *data = dev->data;
231
232 gpio_xlnx_axi_write_data(dev, data->dout);
233 gpio_xlnx_axi_write_tri(dev, data->tri);
234
235 return 0;
236 }
237
238 static const struct gpio_driver_api gpio_xlnx_axi_driver_api = {
239 .pin_configure = gpio_xlnx_axi_pin_configure,
240 .port_get_raw = gpio_xlnx_axi_port_get_raw,
241 .port_set_masked_raw = gpio_xlnx_axi_port_set_masked_raw,
242 .port_set_bits_raw = gpio_xlnx_axi_port_set_bits_raw,
243 .port_clear_bits_raw = gpio_xlnx_axi_port_clear_bits_raw,
244 .port_toggle_bits = gpio_xlnx_axi_port_toggle_bits,
245 .pin_interrupt_configure = gpio_xlnx_axi_pin_interrupt_configure,
246 .manage_callback = gpio_xlnx_axi_manage_callback,
247 .get_pending_int = gpio_xlnx_axi_get_pending_int,
248 };
249
250 #define GPIO_XLNX_AXI_GPIO2_HAS_COMPAT_STATUS_OKAY(n) \
251 UTIL_AND( \
252 DT_NODE_HAS_COMPAT(DT_CHILD(DT_DRV_INST(n), gpio2), \
253 xlnx_xps_gpio_1_00_a_gpio2), \
254 DT_NODE_HAS_STATUS(DT_CHILD(DT_DRV_INST(n), gpio2), \
255 okay) \
256 )
257
258 #define GPIO_XLNX_AXI_GPIO2_COND_INIT(n) \
259 IF_ENABLED(UTIL_AND( \
260 DT_INST_PROP_OR(n, xlnx_is_dual, 1), \
261 GPIO_XLNX_AXI_GPIO2_HAS_COMPAT_STATUS_OKAY(n) \
262 ), \
263 (GPIO_XLNX_AXI_GPIO2_INIT(n)));
264
265 #define GPIO_XLNX_AXI_GPIO2_INIT(n) \
266 static struct gpio_xlnx_axi_data gpio_xlnx_axi_##n##_2_data = { \
267 .dout = DT_INST_PROP_OR(n, xlnx_dout_default_2, 0), \
268 .tri = DT_INST_PROP_OR(n, xlnx_tri_default_2, \
269 GENMASK(MAX_GPIOS - 1, 0)), \
270 }; \
271 \
272 static const struct gpio_xlnx_axi_config \
273 gpio_xlnx_axi_##n##_2_config = { \
274 .common = { \
275 .port_pin_mask = GPIO_PORT_PIN_MASK_FROM_NGPIOS(\
276 DT_INST_PROP_OR(n, xlnx_gpio2_width, \
277 MAX_GPIOS)), \
278 }, \
279 .base = DT_INST_REG_ADDR(n) + GPIO2_DATA_OFFSET, \
280 .all_inputs = DT_INST_PROP_OR(n, xlnx_all_inputs2, 0), \
281 .all_outputs = DT_INST_PROP_OR(n, xlnx_all_outputs2, 0),\
282 }; \
283 \
284 DEVICE_DT_DEFINE(DT_CHILD(DT_DRV_INST(n), gpio2), \
285 &gpio_xlnx_axi_init, \
286 NULL, \
287 &gpio_xlnx_axi_##n##_2_data, \
288 &gpio_xlnx_axi_##n##_2_config, \
289 POST_KERNEL, \
290 CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, \
291 &gpio_xlnx_axi_driver_api);
292
293 #define GPIO_XLNX_AXI_INIT(n) \
294 static struct gpio_xlnx_axi_data gpio_xlnx_axi_##n##_data = { \
295 .dout = DT_INST_PROP_OR(n, xlnx_dout_default, 0), \
296 .tri = DT_INST_PROP_OR(n, xlnx_tri_default, \
297 GENMASK(MAX_GPIOS - 1, 0)), \
298 }; \
299 \
300 static const struct gpio_xlnx_axi_config \
301 gpio_xlnx_axi_##n##_config = { \
302 .common = { \
303 .port_pin_mask = GPIO_PORT_PIN_MASK_FROM_NGPIOS(\
304 DT_INST_PROP_OR(n, xlnx_gpio_width, \
305 MAX_GPIOS)), \
306 }, \
307 .base = DT_INST_REG_ADDR(n), \
308 .all_inputs = DT_INST_PROP_OR(n, xlnx_all_inputs, 0), \
309 .all_outputs = DT_INST_PROP_OR(n, xlnx_all_outputs, 0), \
310 }; \
311 \
312 DEVICE_DT_INST_DEFINE(n, \
313 &gpio_xlnx_axi_init, \
314 NULL, \
315 &gpio_xlnx_axi_##n##_data, \
316 &gpio_xlnx_axi_##n##_config, \
317 POST_KERNEL, \
318 CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, \
319 &gpio_xlnx_axi_driver_api); \
320 GPIO_XLNX_AXI_GPIO2_COND_INIT(n);
321
322 DT_INST_FOREACH_STATUS_OKAY(GPIO_XLNX_AXI_INIT)
323
