1 /*
2 * Copyright (c) 2021 Telink Semiconductor
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include "analog.h"
8
9 #include <device.h>
10 #include <drivers/gpio.h>
11 #include "gpio_utils.h"
12
13
14 /* Driver dts compatibility: telink,b91_gpio */
15 #define DT_DRV_COMPAT telink_b91_gpio
16
17 /* Get GPIO instance */
18 #define GET_GPIO(dev) ((volatile struct gpio_b91_t *) \
19 ((const struct gpio_b91_config *)dev->config)->gpio_base)
20
21 /* Get GPIO configuration */
22 #define GET_CFG(dev) ((const struct gpio_b91_config *)dev->config)
23
24 /* Get GPIO IRQ number defined in dts */
25 #define GET_IRQ_NUM(dev) (((const struct gpio_b91_config *)dev->config)->irq_num)
26
27 /* Get GPIO IRQ priority defined in dts */
28 #define GET_IRQ_PRIORITY(dev) (((const struct gpio_b91_config *)dev->config)->irq_priority)
29
30 /* Get GPIO port number: port A - 0, port B - 1, ..., port F - 5 */
31 #define GET_PORT_NUM(gpio) ((uint8_t)(((uint32_t)gpio - DT_REG_ADDR(DT_NODELABEL(gpioa))) / \
32 DT_REG_SIZE(DT_NODELABEL(gpioa))))
33
34 /* Check that gpio is port C */
35 #define IS_PORT_C(gpio) ((uint32_t)gpio == DT_REG_ADDR(DT_NODELABEL(gpioc)))
36
37 /* Check that gpio is port D */
38 #define IS_PORT_D(gpio) ((uint32_t)gpio == DT_REG_ADDR(DT_NODELABEL(gpiod)))
39
40 /* Check that 'inst' has only 1 interrupt selected in dts */
41 #define IS_INST_IRQ_EN(inst) (DT_NUM_IRQS(DT_DRV_INST(inst)) == 1)
42
43 /* Max pin number per port (pin 0..7) */
44 #define PIN_NUM_MAX ((uint8_t)7u)
45
46 /* IRQ Enable registers */
47 #define reg_irq_risc0_en(i) REG_ADDR8(0x140338 + i)
48 #define reg_irq_risc1_en(i) REG_ADDR8(0x140340 + i)
49
50 /* Pull-up/down resistors */
51 #define GPIO_PIN_UP_DOWN_FLOAT ((uint8_t)0u)
52 #define GPIO_PIN_PULLDOWN_100K ((uint8_t)2u)
53 #define GPIO_PIN_PULLUP_10K ((uint8_t)3u)
54
55 /* GPIO interrupt types */
56 #define INTR_RISING_EDGE ((uint8_t)0u)
57 #define INTR_FALLING_EDGE ((uint8_t)1u)
58 #define INTR_HIGH_LEVEL ((uint8_t)2u)
59 #define INTR_LOW_LEVEL ((uint8_t)3u)
60
61 /* Supported IRQ numbers */
62 #define IRQ_GPIO ((uint8_t)25u)
63 #define IRQ_GPIO2_RISC0 ((uint8_t)26u)
64 #define IRQ_GPIO2_RISC1 ((uint8_t)27u)
65
66
67 /* B91 GPIO registers structure */
68 struct gpio_b91_t {
69 uint8_t input; /* Input: read GPI input */
70 uint8_t ie; /* IE: input enable, high active. 1: enable, 0: disable */
71 uint8_t oen; /* OEN: output enable, low active. 0: enable, 1: disable */
72 uint8_t output; /* Output: configure GPIO output */
73 uint8_t polarity; /* Polarity: interrupt polarity: rising, falling */
74 uint8_t ds; /* DS: drive strength. 1: maximum (default), 0: minimal */
75 uint8_t actas_gpio; /* Act as GPIO: enable (1) or disable (0) GPIO function */
76 uint8_t irq_en; /* Act as GPIO: enable (1) or disable (0) GPIO function */
77 };
78
79 /* GPIO driver configuration structure */
80 struct gpio_b91_config {
81 struct gpio_driver_config common;
82 uint32_t gpio_base;
83 uint8_t irq_num;
84 uint8_t irq_priority;
85 void (*pirq_connect)(void);
86 };
87
88 /* GPIO driver data structure */
89 struct gpio_b91_data {
90 struct gpio_driver_data common; /* driver data */
91 sys_slist_t callbacks; /* list of callbacks */
92 };
93
94
95 /* Set IRQ Enable bit based on IRQ number */
gpiob_b91_irq_en_set(const struct device * dev,gpio_pin_t pin)96 static inline void gpiob_b91_irq_en_set(const struct device *dev, gpio_pin_t pin)
97 {
98 uint8_t irq = GET_IRQ_NUM(dev);
99
100 volatile struct gpio_b91_t *gpio = GET_GPIO(dev);
101
102 if (irq == IRQ_GPIO) {
103 BM_SET(gpio->irq_en, BIT(pin));
104 } else if (irq == IRQ_GPIO2_RISC0) {
105 BM_SET(reg_irq_risc0_en(GET_PORT_NUM(gpio)), BIT(pin));
106 } else if (irq == IRQ_GPIO2_RISC1) {
107 BM_SET(reg_irq_risc1_en(GET_PORT_NUM(gpio)), BIT(pin));
108 } else {
109 __ASSERT(false, "Not supported GPIO IRQ number.");
110 }
111 }
112
113 /* Clear IRQ Enable bit based on IRQ number */
gpiob_b91_irq_en_clr(const struct device * dev,gpio_pin_t pin)114 static inline void gpiob_b91_irq_en_clr(const struct device *dev, gpio_pin_t pin)
115 {
116 uint8_t irq = GET_IRQ_NUM(dev);
117 volatile struct gpio_b91_t *gpio = GET_GPIO(dev);
118
119 if (irq == IRQ_GPIO) {
120 BM_CLR(gpio->irq_en, BIT(pin));
121 } else if (irq == IRQ_GPIO2_RISC0) {
122 BM_CLR(reg_irq_risc0_en(GET_PORT_NUM(gpio)), BIT(pin));
123 } else if (irq == IRQ_GPIO2_RISC1) {
124 BM_CLR(reg_irq_risc1_en(GET_PORT_NUM(gpio)), BIT(pin));
125 }
126 }
127
128 /* Get IRQ Enable register value */
gpio_b91_irq_en_get(const struct device * dev)129 static inline uint8_t gpio_b91_irq_en_get(const struct device *dev)
130 {
131 uint8_t status = 0;
132 uint8_t irq = GET_IRQ_NUM(dev);
133 volatile struct gpio_b91_t *gpio = GET_GPIO(dev);
134
135 if (irq == IRQ_GPIO) {
136 status = gpio->irq_en;
137 } else if (irq == IRQ_GPIO2_RISC0) {
138 status = reg_irq_risc0_en(GET_PORT_NUM(gpio));
139 } else if (irq == IRQ_GPIO2_RISC1) {
140 status = reg_irq_risc1_en(GET_PORT_NUM(gpio));
141 }
142
143 return status;
144 }
145
146 /* Clear IRQ Status bit */
gpio_b91_irq_status_clr(uint8_t irq)147 static inline void gpio_b91_irq_status_clr(uint8_t irq)
148 {
149 gpio_irq_status_e status = 0;
150
151 if (irq == IRQ_GPIO) {
152 status = FLD_GPIO_IRQ_CLR;
153 } else if (irq == IRQ_GPIO2_RISC0) {
154 status = FLD_GPIO_IRQ_GPIO2RISC0_CLR;
155 } else if (irq == IRQ_GPIO2_RISC1) {
156 status = FLD_GPIO_IRQ_GPIO2RISC1_CLR;
157 }
158
159 reg_gpio_irq_clr = status;
160 }
161
162 /* Set pin's irq type */
gpio_b91_irq_set(const struct device * dev,gpio_pin_t pin,uint8_t trigger_type)163 void gpio_b91_irq_set(const struct device *dev, gpio_pin_t pin,
164 uint8_t trigger_type)
165 {
166 uint8_t irq_lvl = 0;
167 uint8_t irq_mask = 0;
168 uint8_t irq_num = GET_IRQ_NUM(dev);
169 uint8_t irq_prioriy = GET_IRQ_PRIORITY(dev);
170 volatile struct gpio_b91_t *gpio = GET_GPIO(dev);
171
172 /* Get level and mask bsed on IRQ number */
173 if (irq_num == IRQ_GPIO) {
174 irq_lvl = FLD_GPIO_IRQ_LVL_GPIO;
175 irq_mask = FLD_GPIO_IRQ_MASK_GPIO;
176 } else if (irq_num == IRQ_GPIO2_RISC0) {
177 irq_lvl = FLD_GPIO_IRQ_LVL_GPIO2RISC0;
178 irq_mask = FLD_GPIO_IRQ_MASK_GPIO2RISC0;
179 } else if (irq_num == IRQ_GPIO2_RISC1) {
180 irq_lvl = FLD_GPIO_IRQ_LVL_GPIO2RISC1;
181 irq_mask = FLD_GPIO_IRQ_MASK_GPIO2RISC1;
182 }
183
184 /* Set polarity and level */
185 switch (trigger_type) {
186 case INTR_RISING_EDGE:
187 BM_CLR(gpio->polarity, BIT(pin));
188 BM_CLR(reg_gpio_irq_risc_mask, irq_lvl);
189 break;
190
191 case INTR_FALLING_EDGE:
192 BM_SET(gpio->polarity, BIT(pin));
193 BM_CLR(reg_gpio_irq_risc_mask, irq_lvl);
194 break;
195
196 case INTR_HIGH_LEVEL:
197 BM_CLR(gpio->polarity, BIT(pin));
198 BM_SET(reg_gpio_irq_risc_mask, irq_lvl);
199 break;
200
201 case INTR_LOW_LEVEL:
202 BM_SET(gpio->polarity, BIT(pin));
203 BM_SET(reg_gpio_irq_risc_mask, irq_lvl);
204 break;
205 }
206
207 if (irq_num == IRQ_GPIO) {
208 reg_gpio_irq_ctrl |= FLD_GPIO_CORE_INTERRUPT_EN;
209 }
210 gpio_b91_irq_status_clr(irq_num);
211 BM_SET(reg_gpio_irq_risc_mask, irq_mask);
212
213 /* Enable peripheral interrupt */
214 gpiob_b91_irq_en_set(dev, pin);
215
216 /* Enable PLIC interrupt */
217 riscv_plic_irq_enable(irq_num);
218 riscv_plic_set_priority(irq_num, irq_prioriy);
219 }
220
221 /* Set pin's pull-up/down resistor */
gpio_b91_up_down_res_set(volatile struct gpio_b91_t * gpio,gpio_pin_t pin,uint8_t up_down_res)222 static void gpio_b91_up_down_res_set(volatile struct gpio_b91_t *gpio,
223 gpio_pin_t pin,
224 uint8_t up_down_res)
225 {
226 uint8_t val;
227 uint8_t mask;
228 uint8_t analog_reg;
229
230 pin = BIT(pin);
231 val = up_down_res & 0x03;
232 analog_reg = 0x0e + (GET_PORT_NUM(gpio) << 1) + ((pin & 0xf0) ? 1 : 0);
233
234 if (pin & 0x11) {
235 val = val << 0;
236 mask = 0xfc;
237 } else if (pin & 0x22) {
238 val = val << 2;
239 mask = 0xf3;
240 } else if (pin & 0x44) {
241 val = val << 4;
242 mask = 0xcf;
243 } else if (pin & 0x88) {
244 val = val << 6;
245 mask = 0x3f;
246 } else {
247 return;
248 }
249
250 analog_write_reg8(analog_reg, (analog_read_reg8(analog_reg) & mask) | val);
251 }
252
253 /* Config Pin pull-up / pull-down resistors */
gpio_b91_config_up_down_res(volatile struct gpio_b91_t * gpio,gpio_pin_t pin,gpio_flags_t flags)254 static void gpio_b91_config_up_down_res(volatile struct gpio_b91_t *gpio,
255 gpio_pin_t pin,
256 gpio_flags_t flags)
257 {
258 if ((flags & GPIO_PULL_UP) != 0) {
259 gpio_b91_up_down_res_set(gpio, pin, GPIO_PIN_PULLUP_10K);
260 } else if ((flags & GPIO_PULL_DOWN) != 0) {
261 gpio_b91_up_down_res_set(gpio, pin, GPIO_PIN_PULLDOWN_100K);
262 } else {
263 gpio_b91_up_down_res_set(gpio, pin, GPIO_PIN_UP_DOWN_FLOAT);
264 }
265 }
266
267 /* Config Pin In/Out direction */
gpio_b91_config_in_out(volatile struct gpio_b91_t * gpio,gpio_pin_t pin,gpio_flags_t flags)268 static void gpio_b91_config_in_out(volatile struct gpio_b91_t *gpio,
269 gpio_pin_t pin,
270 gpio_flags_t flags)
271 {
272 uint8_t ie_addr = 0;
273
274 /* Port C and D Input Enable registers are located in another place: analog */
275 if (IS_PORT_C(gpio)) {
276 ie_addr = areg_gpio_pc_ie;
277 } else if (IS_PORT_D(gpio)) {
278 ie_addr = areg_gpio_pd_ie;
279 }
280
281 /* Enable/disable output */
282 WRITE_BIT(gpio->oen, pin, ~flags & GPIO_OUTPUT);
283
284 /* Enable/disable input */
285 if (ie_addr != 0) {
286 /* Port C and D are located in analog space */
287 if (flags & GPIO_INPUT) {
288 analog_write_reg8(ie_addr, analog_read_reg8(ie_addr) | BIT(pin));
289 } else {
290 analog_write_reg8(ie_addr, analog_read_reg8(ie_addr) & (~BIT(pin)));
291 }
292 } else {
293 /* Input Enable registers of all other ports are located in common GPIO space */
294 WRITE_BIT(gpio->ie, pin, flags & GPIO_INPUT);
295 }
296 }
297
298 /* GPIO driver initialization */
gpio_b91_init(const struct device * dev)299 static int gpio_b91_init(const struct device *dev)
300 {
301 const struct gpio_b91_config *cfg = GET_CFG(dev);
302
303 cfg->pirq_connect();
304
305 return 0;
306 }
307
308 /* API implementation: pin_configure */
gpio_b91_pin_configure(const struct device * dev,gpio_pin_t pin,gpio_flags_t flags)309 static int gpio_b91_pin_configure(const struct device *dev,
310 gpio_pin_t pin,
311 gpio_flags_t flags)
312 {
313 volatile struct gpio_b91_t *gpio = GET_GPIO(dev);
314
315 /* Check input parameters: pin number */
316 if (pin > PIN_NUM_MAX) {
317 return -ENOTSUP;
318 }
319
320 /* Check input parameters: open-source and open-drain */
321 if ((flags & GPIO_SINGLE_ENDED) != 0) {
322 return -ENOTSUP;
323 }
324
325 /* Check input parameters: simultaneous in/out mode */
326 if ((flags & GPIO_OUTPUT) && (flags & GPIO_INPUT)) {
327 return -ENOTSUP;
328 }
329
330 /* Strengths not implemented */
331 if ((flags & (GPIO_DS_ALT_LOW | GPIO_DS_ALT_HIGH)) != 0) {
332 return -ENOTSUP;
333 }
334
335 /* Set GPIO init state if defined to avoid glitches */
336 if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0) {
337 gpio->output |= BIT(pin);
338 } else if ((flags & GPIO_OUTPUT_INIT_LOW) != 0) {
339 gpio->output &= ~BIT(pin);
340 }
341
342 /* GPIO function enable */
343 WRITE_BIT(gpio->actas_gpio, BIT(pin), 1);
344
345 /* Set GPIO pull-up / pull-down resistors */
346 gpio_b91_config_up_down_res(gpio, pin, flags);
347
348 /* Enable/disable input/output */
349 gpio_b91_config_in_out(gpio, pin, flags);
350
351 return 0;
352 }
353
354 /* API implementation: port_get_raw */
gpio_b91_port_get_raw(const struct device * dev,gpio_port_value_t * value)355 static int gpio_b91_port_get_raw(const struct device *dev,
356 gpio_port_value_t *value)
357 {
358 volatile struct gpio_b91_t *gpio = GET_GPIO(dev);
359
360 *value = gpio->input;
361
362 return 0;
363 }
364
365 /* API implementation: port_set_masked_raw */
gpio_b91_port_set_masked_raw(const struct device * dev,gpio_port_pins_t mask,gpio_port_value_t value)366 static int gpio_b91_port_set_masked_raw(const struct device *dev,
367 gpio_port_pins_t mask,
368 gpio_port_value_t value)
369 {
370 volatile struct gpio_b91_t *gpio = GET_GPIO(dev);
371
372 gpio->output = (gpio->output & ~mask) | (value & mask);
373
374 return 0;
375 }
376
377 /* API implementation: port_set_bits_raw */
gpio_b91_port_set_bits_raw(const struct device * dev,gpio_port_pins_t mask)378 static int gpio_b91_port_set_bits_raw(const struct device *dev,
379 gpio_port_pins_t mask)
380 {
381 volatile struct gpio_b91_t *gpio = GET_GPIO(dev);
382
383 gpio->output |= mask;
384
385 return 0;
386 }
387
388 /* API implementation: port_clear_bits_raw */
gpio_b91_port_clear_bits_raw(const struct device * dev,gpio_port_pins_t mask)389 static int gpio_b91_port_clear_bits_raw(const struct device *dev,
390 gpio_port_pins_t mask)
391 {
392 volatile struct gpio_b91_t *gpio = GET_GPIO(dev);
393
394 gpio->output &= ~mask;
395
396 return 0;
397 }
398
399 /* API implementation: port_toggle_bits */
gpio_b91_port_toggle_bits(const struct device * dev,gpio_port_pins_t mask)400 static int gpio_b91_port_toggle_bits(const struct device *dev,
401 gpio_port_pins_t mask)
402 {
403 volatile struct gpio_b91_t *gpio = GET_GPIO(dev);
404
405 gpio->output ^= mask;
406
407 return 0;
408 }
409
410 /* API implementation: interrupts handler */
411 #if IS_INST_IRQ_EN(0) || IS_INST_IRQ_EN(1) || IS_INST_IRQ_EN(2) || \
412 IS_INST_IRQ_EN(3) || IS_INST_IRQ_EN(4)
gpio_b91_irq_handler(const struct device * dev)413 static void gpio_b91_irq_handler(const struct device *dev)
414 {
415 struct gpio_b91_data *data = dev->data;
416 uint8_t irq = GET_IRQ_NUM(dev);
417 uint8_t status = gpio_b91_irq_en_get(dev);
418
419 gpio_b91_irq_status_clr(irq);
420 gpio_fire_callbacks(&data->callbacks, dev, status);
421 }
422 #endif
423
424 /* API implementation: pin_interrupt_configure */
gpio_b91_pin_interrupt_configure(const struct device * dev,gpio_pin_t pin,enum gpio_int_mode mode,enum gpio_int_trig trig)425 static int gpio_b91_pin_interrupt_configure(const struct device *dev,
426 gpio_pin_t pin,
427 enum gpio_int_mode mode,
428 enum gpio_int_trig trig)
429 {
430 int ret_status = 0;
431
432 switch (mode) {
433 case GPIO_INT_MODE_DISABLED: /* GPIO interrupt disable */
434 gpiob_b91_irq_en_clr(dev, pin);
435 break;
436
437 case GPIO_INT_MODE_LEVEL:
438 if (trig == GPIO_INT_TRIG_HIGH) { /* GPIO interrupt High level */
439 gpio_b91_irq_set(dev, pin, INTR_HIGH_LEVEL);
440 } else if (trig == GPIO_INT_TRIG_LOW) { /* GPIO interrupt Low level */
441 gpio_b91_irq_set(dev, pin, INTR_LOW_LEVEL);
442 } else {
443 ret_status = -ENOTSUP;
444 }
445 break;
446
447 case GPIO_INT_MODE_EDGE:
448 if (trig == GPIO_INT_TRIG_HIGH) { /* GPIO interrupt Rising edge */
449 gpio_b91_irq_set(dev, pin, INTR_RISING_EDGE);
450 } else if (trig == GPIO_INT_TRIG_LOW) { /* GPIO interrupt Falling edge */
451 gpio_b91_irq_set(dev, pin, INTR_FALLING_EDGE);
452 } else {
453 ret_status = -ENOTSUP;
454 }
455 break;
456
457 default:
458 ret_status = -ENOTSUP;
459 break;
460 }
461
462 return ret_status;
463 }
464
465 /* API implementation: manage_callback */
gpio_b91_manage_callback(const struct device * dev,struct gpio_callback * callback,bool set)466 static int gpio_b91_manage_callback(const struct device *dev,
467 struct gpio_callback *callback,
468 bool set)
469 {
470 struct gpio_b91_data *data = dev->data;
471
472 return gpio_manage_callback(&data->callbacks, callback, set);
473 }
474
475 /* GPIO driver APIs structure */
476 static const struct gpio_driver_api gpio_b91_driver_api = {
477 .pin_configure = gpio_b91_pin_configure,
478 .port_get_raw = gpio_b91_port_get_raw,
479 .port_set_masked_raw = gpio_b91_port_set_masked_raw,
480 .port_set_bits_raw = gpio_b91_port_set_bits_raw,
481 .port_clear_bits_raw = gpio_b91_port_clear_bits_raw,
482 .port_toggle_bits = gpio_b91_port_toggle_bits,
483 .pin_interrupt_configure = gpio_b91_pin_interrupt_configure,
484 .manage_callback = gpio_b91_manage_callback
485 };
486
487 /* If instance 0 is present and has interrupt enabled, connect IRQ */
488 #if DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) > 0
gpio_b91_irq_connect_0(void)489 static void gpio_b91_irq_connect_0(void)
490 {
491 #if IS_INST_IRQ_EN(0)
492 IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority),
493 gpio_b91_irq_handler,
494 DEVICE_DT_INST_GET(0), 0);
495 #endif
496 }
497 #endif
498
499 /* If instance 1 is present and has interrupt enabled, connect IRQ */
500 #if DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) > 1
gpio_b91_irq_connect_1(void)501 static void gpio_b91_irq_connect_1(void)
502 {
503 #if IS_INST_IRQ_EN(1)
504 IRQ_CONNECT(DT_INST_IRQN(1), DT_INST_IRQ(1, priority),
505 gpio_b91_irq_handler,
506 DEVICE_DT_INST_GET(1), 0);
507 #endif
508 }
509 #endif
510
511 /* If instance 2 is present and has interrupt enabled, connect IRQ */
512 #if DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) > 2
gpio_b91_irq_connect_2(void)513 static void gpio_b91_irq_connect_2(void)
514 {
515 #if IS_INST_IRQ_EN(2)
516 IRQ_CONNECT(DT_INST_IRQN(2), DT_INST_IRQ(2, priority),
517 gpio_b91_irq_handler,
518 DEVICE_DT_INST_GET(2), 0);
519 #endif
520 }
521 #endif
522
523 /* If instance 3 is present and has interrupt enabled, connect IRQ */
524 #if DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) > 3
gpio_b91_irq_connect_3(void)525 static void gpio_b91_irq_connect_3(void)
526 {
527 #if IS_INST_IRQ_EN(3)
528 IRQ_CONNECT(DT_INST_IRQN(3), DT_INST_IRQ(3, priority),
529 gpio_b91_irq_handler,
530 DEVICE_DT_INST_GET(3), 0);
531 #endif
532 }
533 #endif
534
535 /* If instance 4 is present and has interrupt enabled, connect IRQ */
536 #if DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) > 4
gpio_b91_irq_connect_4(void)537 static void gpio_b91_irq_connect_4(void)
538 {
539 #if IS_INST_IRQ_EN(4)
540 IRQ_CONNECT(DT_INST_IRQN(4), DT_INST_IRQ(4, priority),
541 gpio_b91_irq_handler,
542 DEVICE_DT_INST_GET(4), 0);
543 #endif
544 }
545 #endif
546
547 /* GPIO driver registration */
548 #define GPIO_B91_INIT(n) \
549 static const struct gpio_b91_config gpio_b91_config_##n = { \
550 .common = { \
551 .port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(n) \
552 }, \
553 .gpio_base = DT_INST_REG_ADDR(n), \
554 .irq_num = DT_INST_IRQN(n), \
555 .irq_priority = DT_INST_IRQ(n, priority), \
556 .pirq_connect = gpio_b91_irq_connect_##n \
557 }; \
558 static struct gpio_b91_data gpio_b91_data_##n; \
559 \
560 DEVICE_DT_INST_DEFINE(n, gpio_b91_init, \
561 NULL, \
562 &gpio_b91_data_##n, \
563 &gpio_b91_config_##n, \
564 POST_KERNEL, \
565 CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, \
566 &gpio_b91_driver_api);
567
568 DT_INST_FOREACH_STATUS_OKAY(GPIO_B91_INIT)
569
