1 /*
2 * Copyright (c) 2019 Linaro Limited
3 * Copyright (c) 2020 STMicroelectronics
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8 #define LOG_DOMAIN flash_stm32wb
9 #define LOG_LEVEL CONFIG_FLASH_LOG_LEVEL
10 #include <logging/log.h>
11 LOG_MODULE_REGISTER(LOG_DOMAIN);
12
13 #include <kernel.h>
14 #include <device.h>
15 #include <string.h>
16 #include <drivers/flash.h>
17 #include <init.h>
18 #include <soc.h>
19 #include <sys/__assert.h>
20
21 #include "flash_stm32.h"
22 #include "stm32_hsem.h"
23 #if defined(CONFIG_BT)
24 #include "shci.h"
25 #endif
26
27 #define STM32WBX_PAGE_SHIFT 12
28
29 /* offset and len must be aligned on 8 for write,
30 * positive and not beyond end of flash
31 */
flash_stm32_valid_range(const struct device * dev,off_t offset,uint32_t len,bool write)32 bool flash_stm32_valid_range(const struct device *dev, off_t offset,
33 uint32_t len,
34 bool write)
35 {
36 return (!write || (offset % 8 == 0 && len % 8 == 0U)) &&
37 flash_stm32_range_exists(dev, offset, len);
38 }
39
40 /*
41 * Up to 255 4K pages
42 */
get_page(off_t offset)43 static uint32_t get_page(off_t offset)
44 {
45 return offset >> STM32WBX_PAGE_SHIFT;
46 }
47
flush_cache(FLASH_TypeDef * regs)48 static inline void flush_cache(FLASH_TypeDef *regs)
49 {
50 if (regs->ACR & FLASH_ACR_DCEN) {
51 regs->ACR &= ~FLASH_ACR_DCEN;
52 /* Datasheet: DCRST: Data cache reset
53 * This bit can be written only when thes data cache is disabled
54 */
55 regs->ACR |= FLASH_ACR_DCRST;
56 regs->ACR &= ~FLASH_ACR_DCRST;
57 regs->ACR |= FLASH_ACR_DCEN;
58 }
59
60 if (regs->ACR & FLASH_ACR_ICEN) {
61 regs->ACR &= ~FLASH_ACR_ICEN;
62 /* Datasheet: ICRST: Instruction cache reset :
63 * This bit can be written only when the instruction cache
64 * is disabled
65 */
66 regs->ACR |= FLASH_ACR_ICRST;
67 regs->ACR &= ~FLASH_ACR_ICRST;
68 regs->ACR |= FLASH_ACR_ICEN;
69 }
70 }
71
write_dword(const struct device * dev,off_t offset,uint64_t val)72 static int write_dword(const struct device *dev, off_t offset, uint64_t val)
73 {
74 volatile uint32_t *flash = (uint32_t *)(offset + CONFIG_FLASH_BASE_ADDRESS);
75 FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
76 uint32_t tmp;
77 int ret, rc;
78 uint32_t cpu1_sem_status;
79 uint32_t cpu2_sem_status = 0;
80 uint32_t key;
81
82 /* if the control register is locked, do not fail silently */
83 if (regs->CR & FLASH_CR_LOCK) {
84 return -EIO;
85 }
86
87 /* Check if this double word is erased */
88 if (flash[0] != 0xFFFFFFFFUL ||
89 flash[1] != 0xFFFFFFFFUL) {
90 return -EIO;
91 }
92
93 ret = flash_stm32_check_status(dev);
94 if (ret < 0) {
95 return -EIO;
96 }
97
98 /* Implementation of STM32 AN5289, proposed in STM32WB Cube Application
99 * BLE_RfWithFlash
100 * https://github.com/STMicroelectronics/STM32CubeWB/tree/master/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_RfWithFlash
101 */
102
103 do {
104 /**
105 * When the PESD bit mechanism is used by CPU2 to protect its
106 * timing, the PESD bit should be polled here.
107 * If the PESD is set, the CPU1 will be stalled when reading
108 * literals from an ISR that may occur after the flash
109 * processing has been requested but suspended due to the PESD
110 * bit.
111 *
112 * Note: This code is required only when the PESD mechanism is
113 * used to protect the CPU2 timing.
114 * However, keeping that code make it compatible with both
115 * mechanisms.
116 */
117 while (LL_FLASH_IsActiveFlag_OperationSuspended())
118 ;
119
120 /* Enter critical section */
121 key = irq_lock();
122
123 /**
124 * Depending on the application implementation, in case a
125 * multitasking is possible with an OS, it should be checked
126 * here if another task in the application disallowed flash
127 * processing to protect some latency in critical code
128 * execution.
129 * When flash processing is ongoing, the CPU cannot access the
130 * flash anymore.Trying to access the flash during that time
131 * stalls the CPU.
132 * The only way for CPU1 to disallow flash processing is to
133 * take CFG_HW_BLOCK_FLASH_REQ_BY_CPU1_SEMID.
134 */
135 cpu1_sem_status = LL_HSEM_GetStatus(HSEM,
136 CFG_HW_BLOCK_FLASH_REQ_BY_CPU1_SEMID);
137 if (cpu1_sem_status == 0) {
138 /**
139 * Check now if the CPU2 disallows flash processing to
140 * protect its timing. If the semaphore is locked, the
141 * CPU2 does not allow flash processing
142 *
143 * Note: By default, the CPU2 uses the PESD mechanism
144 * to protect its timing, therefore, it is useless to
145 * get/release the semaphore.
146 *
147 * However, keeping that code make it compatible with
148 * bothmechanisms.
149 * The protection by semaphore is enabled on CPU2 side
150 * with the command SHCI_C2_SetFlashActivityControl()
151 *
152 */
153 cpu2_sem_status = LL_HSEM_1StepLock(HSEM,
154 CFG_HW_BLOCK_FLASH_REQ_BY_CPU2_SEMID);
155 if (cpu2_sem_status == 0) {
156 /**
157 * When CFG_HW_BLOCK_FLASH_REQ_BY_CPU2_SEMID is
158 * taken, it is allowed to only write one
159 * single 64bits data.
160 * When several 64bits data need to be erased,
161 * the application shall first exit from the
162 * critical section and try again.
163 */
164 /* Set the PG bit */
165 regs->CR |= FLASH_CR_PG;
166
167 /* Flush the register write */
168 tmp = regs->CR;
169
170 /* Perform the data write operation at desired
171 * memory address
172 */
173 flash[0] = (uint32_t)val;
174 flash[1] = (uint32_t)(val >> 32);
175
176 /**
177 * Release the semaphore to give the
178 * opportunity to CPU2 to protect its timing
179 * versus the next flash operation by taking
180 * this semaphore.
181 * Note that the CPU2 is polling on this
182 * semaphore so CPU1 shall release it as fast
183 * as possible.
184 * This is why this code is protected by a
185 * critical section.
186 */
187 LL_HSEM_ReleaseLock(HSEM,
188 CFG_HW_BLOCK_FLASH_REQ_BY_CPU2_SEMID,
189 0);
190 }
191 }
192
193 /* Exit critical section */
194 irq_unlock(key);
195
196 } while (cpu2_sem_status || cpu1_sem_status);
197
198 /* Wait until the BSY bit is cleared */
199 rc = flash_stm32_wait_flash_idle(dev);
200
201 /* Clear the PG bit */
202 regs->CR &= (~FLASH_CR_PG);
203
204 return rc;
205 }
206
erase_page(const struct device * dev,uint32_t page)207 static int erase_page(const struct device *dev, uint32_t page)
208 {
209 uint32_t cpu1_sem_status;
210 uint32_t cpu2_sem_status = 0;
211 uint32_t key;
212
213 FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
214 int rc;
215
216 /* if the control register is locked, do not fail silently */
217 if (regs->CR & FLASH_CR_LOCK) {
218 return -EIO;
219 }
220
221 /* Check that no Flash memory operation is ongoing */
222 rc = flash_stm32_wait_flash_idle(dev);
223 if (rc < 0) {
224 return rc;
225 }
226
227 /*
228 * If an erase operation in Flash memory also concerns data in the data
229 * or instruction cache, the user has to ensure that these data
230 * are rewritten before they are accessed during code execution.
231 */
232 flush_cache(regs);
233
234 /* Implementation of STM32 AN5289, proposed in STM32WB Cube Application
235 * BLE_RfWithFlash
236 * https://github.com/STMicroelectronics/STM32CubeWB/tree/master/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_RfWithFlash
237 */
238
239 do {
240 /**
241 * When the PESD bit mechanism is used by CPU2 to protect its
242 * timing, the PESD bit should be polled here.
243 * If the PESD is set, the CPU1 will be stalled when reading
244 * literals from an ISR that may occur after the flash
245 * processing has been requested but suspended due to the PESD
246 * bit.
247 *
248 * Note: This code is required only when the PESD mechanism is
249 * used to protect the CPU2 timing.
250 * However, keeping that code make it compatible with both
251 * mechanisms.
252 */
253 while (LL_FLASH_IsActiveFlag_OperationSuspended())
254 ;
255
256 /* Enter critical section */
257 key = irq_lock();
258
259 /**
260 * Depending on the application implementation, in case a
261 * multitasking is possible with an OS, it should be checked
262 * here if another task in the application disallowed flash
263 * processing to protect some latency in critical code
264 * execution.
265 * When flash processing is ongoing, the CPU cannot access the
266 * flash anymore.Trying to access the flash during that time
267 * stalls the CPU.
268 * The only way for CPU1 to disallow flash processing is to
269 * take CFG_HW_BLOCK_FLASH_REQ_BY_CPU1_SEMID.
270 */
271 cpu1_sem_status = LL_HSEM_GetStatus(HSEM,
272 CFG_HW_BLOCK_FLASH_REQ_BY_CPU1_SEMID);
273 if (cpu1_sem_status == 0) {
274 /**
275 * Check now if the CPU2 disallows flash processing to
276 * protect its timing. If the semaphore is locked, the
277 * CPU2 does not allow flash processing
278 *
279 * Note: By default, the CPU2 uses the PESD mechanism
280 * to protect its timing, therefore, it is useless to
281 * get/release the semaphore.
282 *
283 * However, keeping that code make it compatible with
284 * bothmechanisms.
285 * The protection by semaphore is enabled on CPU2 side
286 * with the command SHCI_C2_SetFlashActivityControl()
287 *
288 */
289 cpu2_sem_status = LL_HSEM_1StepLock(HSEM,
290 CFG_HW_BLOCK_FLASH_REQ_BY_CPU2_SEMID);
291 if (cpu2_sem_status == 0) {
292 /**
293 * When CFG_HW_BLOCK_FLASH_REQ_BY_CPU2_SEMID is
294 * taken, it is allowed to only erase one
295 * sector.
296 * When several sectors need to be erased,
297 * the application shall first exit from the
298 * critical section and try again.
299 */
300 regs->CR |= FLASH_CR_PER;
301 regs->CR &= ~FLASH_CR_PNB_Msk;
302 regs->CR |= page << FLASH_CR_PNB_Pos;
303
304 regs->CR |= FLASH_CR_STRT;
305
306 /**
307 * Release the semaphore to give the
308 * opportunity to CPU2 to protect its timing
309 * versus the next flash operation by taking
310 * this semaphore.
311 * Note that the CPU2 is polling on this
312 * semaphore so CPU1 shall release it as fast
313 * as possible.
314 * This is why this code is protected by a
315 * critical section.
316 */
317 LL_HSEM_ReleaseLock(HSEM,
318 CFG_HW_BLOCK_FLASH_REQ_BY_CPU2_SEMID,
319 0);
320 }
321 }
322
323 /* Exit critical section */
324 irq_unlock(key);
325
326 } while (cpu2_sem_status || cpu1_sem_status);
327
328
329 /* Wait for the BSY bit */
330 rc = flash_stm32_wait_flash_idle(dev);
331
332 regs->CR &= ~FLASH_CR_PER;
333
334 return rc;
335 }
336
flash_stm32_block_erase_loop(const struct device * dev,unsigned int offset,unsigned int len)337 int flash_stm32_block_erase_loop(const struct device *dev,
338 unsigned int offset,
339 unsigned int len)
340 {
341 int i, rc = 0;
342
343 #if defined(CONFIG_BT)
344 /**
345 * Notify the CPU2 that some flash erase activity may be executed
346 * On reception of this command, the CPU2 enables the BLE timing
347 * protection versus flash erase processing.
348 * The Erase flash activity will be executed only when the BLE RF is
349 * idle for at least 25ms.
350 * The CPU2 will prevent all flash activity (write or erase) in all
351 * cases when the BL RF Idle is shorter than 25ms.
352 */
353 SHCI_C2_FLASH_EraseActivity(ERASE_ACTIVITY_ON);
354 #endif /* CONFIG_BT */
355
356 i = get_page(offset);
357 for (; i <= get_page(offset + len - 1) ; ++i) {
358 rc = erase_page(dev, i);
359 if (rc < 0) {
360 break;
361 }
362 }
363
364 #if defined(CONFIG_BT)
365 /**
366 * Notify the CPU2 there will be no request anymore to erase the flash
367 * On reception of this command, the CPU2 disables the BLE timing
368 * protection versus flash erase processing
369 */
370 SHCI_C2_FLASH_EraseActivity(ERASE_ACTIVITY_OFF);
371 #endif /* CONFIG_BT */
372
373 return rc;
374 }
375
flash_stm32_write_range(const struct device * dev,unsigned int offset,const void * data,unsigned int len)376 int flash_stm32_write_range(const struct device *dev, unsigned int offset,
377 const void *data, unsigned int len)
378 {
379 int i, rc = 0;
380
381 for (i = 0; i < len; i += 8, offset += 8U) {
382 rc = write_dword(dev, offset,
383 UNALIGNED_GET((const uint64_t *) data + (i >> 3)));
384 if (rc < 0) {
385 return rc;
386 }
387 }
388
389 return rc;
390 }
391
flash_stm32_page_layout(const struct device * dev,const struct flash_pages_layout ** layout,size_t * layout_size)392 void flash_stm32_page_layout(const struct device *dev,
393 const struct flash_pages_layout **layout,
394 size_t *layout_size)
395 {
396 static struct flash_pages_layout stm32wb_flash_layout = {
397 .pages_count = 0,
398 .pages_size = 0,
399 };
400
401 ARG_UNUSED(dev);
402
403 if (stm32wb_flash_layout.pages_count == 0) {
404 stm32wb_flash_layout.pages_count = FLASH_SIZE / FLASH_PAGE_SIZE;
405 stm32wb_flash_layout.pages_size = FLASH_PAGE_SIZE;
406 }
407
408 *layout = &stm32wb_flash_layout;
409 *layout_size = 1;
410 }
411
flash_stm32_check_status(const struct device * dev)412 int flash_stm32_check_status(const struct device *dev)
413 {
414 FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
415 uint32_t error = 0;
416
417 /* Save Flash errors */
418 error = (regs->SR & FLASH_FLAG_SR_ERRORS);
419 error |= (regs->ECCR & FLASH_FLAG_ECCC);
420
421 /* Clear systematic Option and Enginneering bits validity error */
422 if (error & FLASH_FLAG_OPTVERR) {
423 regs->SR |= FLASH_FLAG_SR_ERRORS;
424 return 0;
425 }
426
427 if (error) {
428 return -EIO;
429 }
430
431 return 0;
432 }
433
