1 /* 2 * Copyright (c) 2019 Interay Solutions B.V. 3 * Copyright (c) 2019 Oane Kingma 4 * 5 * SPDX-License-Identifier: Apache-2.0 6 */ 7 8 #ifndef ZEPHYR_DRIVERS_ETHERNET_ETH_GECKO_PRIV_H_ 9 #define ZEPHYR_DRIVERS_ETHERNET_ETH_GECKO_PRIV_H_ 10 11 #include <kernel.h> 12 #include <zephyr/types.h> 13 14 #define ETH_GECKO_MTU NET_ETH_MTU 15 16 #define SILABS_OUI_B0 0x00 17 #define SILABS_OUI_B1 0x0B 18 #define SILABS_OUI_B2 0x57 19 20 #define ETH_TX_BUF_SIZE 1536 21 #define ETH_TX_BUF_COUNT 2 22 #define ETH_RX_BUF_SIZE 128 23 #define ETH_RX_BUF_COUNT 32 24 25 #define ETH_BUF_ALIGNMENT 16 26 27 #define ETH_DESC_ALIGNMENT 4 28 29 #define ETH_TX_USED BIT(31) 30 #define ETH_TX_WRAP BIT(30) 31 #define ETH_TX_ERROR BIT(29) 32 #define ETH_TX_UNDERRUN BIT(28) 33 #define ETH_TX_EXHAUSTED BIT(27) 34 #define ETH_TX_NO_CRC BIT(16) 35 #define ETH_TX_LAST BIT(15) 36 #define ETH_TX_LENGTH (2048-1) 37 38 #define ETH_RX_ADDRESS ~(ETH_DESC_ALIGNMENT-1) 39 #define ETH_RX_WRAP BIT(1) 40 #define ETH_RX_OWNERSHIP BIT(0) 41 #define ETH_RX_BROADCAST BIT(31) 42 #define ETH_RX_MULTICAST_HASH BIT(30) 43 #define ETH_RX_UNICAST_HASH BIT(29) 44 #define ETH_RX_EXT_ADDR BIT(28) 45 #define ETH_RX_SAR1 BIT(26) 46 #define ETH_RX_SAR2 BIT(25) 47 #define ETH_RX_SAR3 BIT(24) 48 #define ETH_RX_SAR4 BIT(23) 49 #define ETH_RX_TYPE_ID BIT(22) 50 #define ETH_RX_VLAN_TAG BIT(21) 51 #define ETH_RX_PRIORITY_TAG BIT(20) 52 #define ETH_RX_VLAN_PRIORITY (0x7UL<<17) 53 #define ETH_RX_CFI BIT(16) 54 #define ETH_RX_EOF BIT(15) 55 #define ETH_RX_SOF BIT(14) 56 #define ETH_RX_OFFSET (0x3UL<<12) 57 #define ETH_RX_LENGTH (4096-1) 58 59 #define ETH_RX_ENABLE(base) (base->NETWORKCTRL |= ETH_NETWORKCTRL_ENBRX) 60 #define ETH_RX_DISABLE(base) (base->NETWORKCTRL &= ~ETH_NETWORKCTRL_ENBRX) 61 62 #define ETH_TX_ENABLE(base) (base->NETWORKCTRL |= ETH_NETWORKCTRL_ENBTX) 63 #define ETH_TX_DISABLE(base) (base->NETWORKCTRL &= ~ETH_NETWORKCTRL_ENBTX) 64 65 struct eth_buf_desc { 66 uint32_t address; 67 uint32_t status; 68 }; 69 70 struct eth_gecko_pin_list { 71 struct soc_gpio_pin mdio[2]; 72 struct soc_gpio_pin rmii[7]; 73 }; 74 75 /* Device constant configuration parameters */ 76 struct eth_gecko_dev_cfg { 77 ETH_TypeDef *regs; 78 const struct eth_gecko_pin_list *pin_list; 79 uint32_t pin_list_size; 80 void (*config_func)(void); 81 struct phy_gecko_dev phy; 82 }; 83 84 /* Device run time data */ 85 struct eth_gecko_dev_data { 86 struct net_if *iface; 87 uint8_t mac_addr[6]; 88 struct k_sem tx_sem; 89 struct k_sem rx_sem; 90 91 K_KERNEL_STACK_MEMBER(rx_thread_stack, 92 CONFIG_ETH_GECKO_RX_THREAD_STACK_SIZE); 93 struct k_thread rx_thread; 94 bool link_up; 95 }; 96 97 #define DEV_NAME(dev) ((dev)->name) 98 #define DEV_CFG(dev) \ 99 ((const struct eth_gecko_dev_cfg *)(dev)->config) 100 #define DEV_DATA(dev) \ 101 ((struct eth_gecko_dev_data *)(dev)->data) 102 103 /* PHY Management pins */ 104 #define PIN_PHY_MDC {DT_INST_PROP_BY_IDX(0, location_phy_mdc, 1), \ 105 DT_INST_PROP_BY_IDX(0, location_phy_mdc, 2), gpioModePushPull,\ 106 0} 107 #define PIN_PHY_MDIO {DT_INST_PROP_BY_IDX(0, location_phy_mdio, 1), \ 108 DT_INST_PROP_BY_IDX(0, location_phy_mdio, 2), gpioModePushPull,\ 109 0} 110 111 #define PIN_LIST_PHY {PIN_PHY_MDC, PIN_PHY_MDIO} 112 113 /* RMII pins excluding reference clock, handled by board.c */ 114 #define PIN_RMII_CRSDV {DT_INST_PROP_BY_IDX(0, location_rmii_crs_dv, 1),\ 115 DT_INST_PROP_BY_IDX(0, location_rmii_crs_dv, 2), gpioModeInput, 0} 116 117 #define PIN_RMII_TXD0 {DT_INST_PROP_BY_IDX(0, location_rmii_txd0, 1),\ 118 DT_INST_PROP_BY_IDX(0, location_rmii_txd0, 2), gpioModePushPull, 0} 119 120 #define PIN_RMII_TXD1 {DT_INST_PROP_BY_IDX(0, location_rmii_txd1, 1),\ 121 DT_INST_PROP_BY_IDX(0, location_rmii_txd1, 2), gpioModePushPull, 0} 122 123 #define PIN_RMII_TX_EN {DT_INST_PROP_BY_IDX(0, location_rmii_tx_en, 1),\ 124 DT_INST_PROP_BY_IDX(0, location_rmii_tx_en, 2), gpioModePushPull, 0} 125 126 #define PIN_RMII_RXD0 {DT_INST_PROP_BY_IDX(0, location_rmii_rxd0, 1),\ 127 DT_INST_PROP_BY_IDX(0, location_rmii_rxd0, 2), gpioModeInput, 0} 128 129 #define PIN_RMII_RXD1 {DT_INST_PROP_BY_IDX(0, location_rmii_rxd1, 1),\ 130 DT_INST_PROP_BY_IDX(0, location_rmii_rxd1, 2), gpioModeInput, 0} 131 132 #define PIN_RMII_RX_ER {DT_INST_PROP_BY_IDX(0, location_rmii_rx_er, 1),\ 133 DT_INST_PROP_BY_IDX(0, location_rmii_rx_er, 2), gpioModeInput, 0} 134 135 #define PIN_LIST_RMII {PIN_RMII_CRSDV, PIN_RMII_TXD0, PIN_RMII_TXD1, \ 136 PIN_RMII_TX_EN, PIN_RMII_RXD0, PIN_RMII_RXD1, PIN_RMII_RX_ER} 137 138 /* RMII reference clock is not included in RMII pin set 139 * #define PIN_RMII_REFCLK {DT_INST_PROP_BY_IDX(0, location_rmii_refclk, 1),\ 140 * DT_INST_PROP_BY_IDX(0, location_rmii_refclk, 2), gpioModePushPull, 0} 141 */ 142 143 #endif /* ZEPHYR_DRIVERS_ETHERNET_ETH_GECKO_PRIV_H_ */ 144
