1 /*
2 * Copyright (c) 2019 Intel Corporation
3 * Copyright (c) 2020 Microchip Technology Inc.
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8 #define DT_DRV_COMPAT microchip_xec_espi_saf
9
10 #include <kernel.h>
11 #include <soc.h>
12 #include <errno.h>
13 #include <drivers/espi.h>
14 #include <drivers/espi_saf.h>
15 #include <logging/log.h>
16
17 #include "espi_utils.h"
18 LOG_MODULE_REGISTER(espi_saf, CONFIG_ESPI_LOG_LEVEL);
19
20 /* SAF EC Portal read/write flash access limited to 1-64 bytes */
21 #define MAX_SAF_ECP_BUFFER_SIZE 64ul
22
23 /* 1 second maximum for flash operations */
24 #define MAX_SAF_FLASH_TIMEOUT 125000ul /* 1000ul */
25
26 /* 64 bytes @ 24MHz quad is approx. 6 us */
27 #define SAF_WAIT_INTERVAL 8
28
29 /* After 8 wait intervals yield */
30 #define SAF_YIELD_THRESHOLD 64
31
32 struct espi_isr {
33 uint32_t girq_bit;
34 void (*the_isr)(const struct device *dev);
35 };
36
37 /*
38 * SAF configuration from Device Tree
39 * SAF controller register block base address
40 * QMSPI controller register block base address
41 * SAF communications register block base address
42 * Flash STATUS1 poll timeout in 32KHz periods
43 * Flash consecutive read timeout in units of 20 ns
44 * Delay before first Poll-1 command after suspend in 20 ns units
45 * Hold off suspend for this interval if erase or program in 32KHz periods.
46 * Add delay between Poll STATUS1 commands in 20 ns units.
47 */
48 struct espi_saf_xec_config {
49 uintptr_t saf_base_addr;
50 uintptr_t qmspi_base_addr;
51 uintptr_t saf_comm_base_addr;
52 uint32_t poll_timeout;
53 uint32_t consec_rd_timeout;
54 uint32_t sus_chk_delay;
55 uint16_t sus_rsm_interval;
56 uint16_t poll_interval;
57 };
58
59 struct espi_saf_xec_data {
60 sys_slist_t callbacks;
61 struct k_sem ecp_lock;
62 uint32_t hwstatus;
63 };
64
65 /* convenience defines */
66 #define DEV_CFG(dev) ((const struct espi_saf_xec_config *const)(dev)->config)
67 #define DEV_DATA(dev) ((struct espi_saf_xec_data *const)(dev)->data)
68
69 /* EC portal local flash r/w buffer */
70 static uint32_t slave_mem[MAX_SAF_ECP_BUFFER_SIZE];
71
72 /*
73 * @brief eSPI SAF configuration
74 */
75
mchp_saf_cs_descr_wr(MCHP_SAF_HW_REGS * regs,uint8_t cs,uint32_t val)76 static inline void mchp_saf_cs_descr_wr(MCHP_SAF_HW_REGS *regs, uint8_t cs,
77 uint32_t val)
78 {
79 regs->SAF_CS_OP[cs].OP_DESCR = val;
80 }
81
mchp_saf_poll2_mask_wr(MCHP_SAF_HW_REGS * regs,uint8_t cs,uint16_t val)82 static inline void mchp_saf_poll2_mask_wr(MCHP_SAF_HW_REGS *regs, uint8_t cs,
83 uint16_t val)
84 {
85 LOG_DBG("%s cs: %d mask %x", __func__, cs, val);
86 if (cs == 0) {
87 regs->SAF_CS0_CFG_P2M = val;
88 } else {
89 regs->SAF_CS1_CFG_P2M = val;
90 }
91 }
92
mchp_saf_cm_prefix_wr(MCHP_SAF_HW_REGS * regs,uint8_t cs,uint16_t val)93 static inline void mchp_saf_cm_prefix_wr(MCHP_SAF_HW_REGS *regs, uint8_t cs,
94 uint16_t val)
95 {
96 if (cs == 0) {
97 regs->SAF_CS0_CM_PRF = val;
98 } else {
99 regs->SAF_CS1_CM_PRF = val;
100 }
101 }
102
103 /* busy wait or yield until we have SAF interrupt support */
xec_saf_spin_yield(int * counter)104 static int xec_saf_spin_yield(int *counter)
105 {
106 *counter = *counter + 1;
107
108 if (*counter > MAX_SAF_FLASH_TIMEOUT) {
109 return -ETIMEDOUT;
110 }
111
112 if (*counter > SAF_YIELD_THRESHOLD) {
113 k_yield();
114 } else {
115 k_busy_wait(SAF_WAIT_INTERVAL);
116 }
117
118 return 0;
119 }
120
121 /*
122 * Initialize SAF flash protection regions.
123 * SAF HW implements 17 protection regions.
124 * At least one protection region must be configured to allow
125 * EC access to the local flash through the EC Portal.
126 * Each protection region is composed of 4 32-bit registers
127 * Start bits[19:0] = bits[31:12] region start address (4KB boundaries)
128 * Limit bits[19:0] = bits[31:12] region limit address (4KB boundaries)
129 * Write protect b[7:0] = masters[7:0] allow write/erase. 1=allowed
130 * Read protetc b[7:0] = masters[7:0] allow read. 1=allowed
131 *
132 * This routine configures protection region 0 for full flash array
133 * address range and read-write-erase for all masters.
134 * This routine must be called AFTER the flash configuration size/limit and
135 * threshold registers have been programmed.
136 *
137 * POR default values:
138 * Start = 0x7ffff
139 * Limit = 0
140 * Write Prot = 0x01 Master 0 always granted write/erase
141 * Read Prot = 0x01 Master 0 always granted read
142 *
143 * Sample code configures PR[0]
144 * Start = 0
145 * Limit = 0x7ffff
146 * WR = 0xFF
147 * RD = 0xFF
148 */
saf_protection_regions_init(MCHP_SAF_HW_REGS * regs)149 static void saf_protection_regions_init(MCHP_SAF_HW_REGS *regs)
150 {
151 LOG_DBG("%s", __func__);
152
153 for (size_t n = 0; n < MCHP_ESPI_SAF_PR_MAX; n++) {
154 if (n == 0) {
155 regs->SAF_PROT_RG[0].START = 0U;
156 regs->SAF_PROT_RG[0].LIMIT =
157 regs->SAF_FL_CFG_SIZE_LIM >> 12;
158 regs->SAF_PROT_RG[0].WEBM = MCHP_SAF_MSTR_ALL;
159 regs->SAF_PROT_RG[0].RDBM = MCHP_SAF_MSTR_ALL;
160 } else {
161 regs->SAF_PROT_RG[n].START =
162 MCHP_SAF_PROT_RG_START_DFLT;
163 regs->SAF_PROT_RG[n].LIMIT =
164 MCHP_SAF_PROT_RG_LIMIT_DFLT;
165 regs->SAF_PROT_RG[n].WEBM = 0U;
166 regs->SAF_PROT_RG[n].RDBM = 0U;
167 }
168
169 LOG_DBG("PROT[%d] START %x", n, regs->SAF_PROT_RG[n].START);
170 LOG_DBG("PROT[%d] LIMIT %x", n, regs->SAF_PROT_RG[n].LIMIT);
171 LOG_DBG("PROT[%d] WEBM %x", n, regs->SAF_PROT_RG[n].WEBM);
172 LOG_DBG("PROT[%d] RDBM %x", n, regs->SAF_PROT_RG[n].RDBM);
173 }
174 }
175
qmspi_freq_div(uint32_t freqhz)176 static uint32_t qmspi_freq_div(uint32_t freqhz)
177 {
178 uint32_t fdiv;
179
180 if (freqhz < (MCHP_QMSPI_MIN_FREQ_KHZ * 1000U)) {
181 fdiv = 0U; /* freq divider field -> 256 */
182 } else if (freqhz >= (MCHP_QMSPI_MAX_FREQ_KHZ * 1000U)) {
183 fdiv = 1U;
184 } else {
185 /* truncation produces next higher integer frequency */
186 fdiv = MCHP_QMSPI_INPUT_CLOCK_FREQ_HZ / freqhz;
187 }
188
189 fdiv &= MCHP_QMSPI_M_FDIV_MASK0;
190 fdiv <<= MCHP_QMSPI_M_FDIV_POS;
191
192 return fdiv;
193 }
194
195 /*
196 * Take over and re-initialize QMSPI for use by SAF HW engine.
197 * When SAF is activated, QMSPI registers are controlled by SAF
198 * HW engine. CPU no longer has access to QMSPI registers.
199 * 1. Save QMSPI driver frequency divider, SPI signalling mode, and
200 * chip select timing.
201 * 2. Put QMSPI controller in a known state by performing a soft reset.
202 * 3. Clear QMSPI GIRQ status
203 * 4. Configure QMSPI interface control for SAF.
204 * 5. Load flash device independent (generic) descriptors.
205 * 6. Enable transfer done interrupt in QMSPI
206 * 7. Enable QMSPI SAF mode
207 * 8. If user configuration overrides frequency, signalling mode,
208 * or chip select timing derive user values.
209 * 9. Program QMSPI MODE and CSTIM registers with activate set.
210 */
saf_qmspi_init(const struct espi_saf_xec_config * xcfg,const struct espi_saf_cfg * cfg)211 static int saf_qmspi_init(const struct espi_saf_xec_config *xcfg,
212 const struct espi_saf_cfg *cfg)
213 {
214 uint32_t qmode, cstim, n;
215 QMSPI_Type *regs = (QMSPI_Type *)xcfg->qmspi_base_addr;
216 const struct espi_saf_hw_cfg *hwcfg = &cfg->hwcfg;
217
218 qmode = regs->MODE;
219 if (!(qmode & MCHP_QMSPI_M_ACTIVATE)) {
220 return -EAGAIN;
221 }
222
223 qmode = regs->MODE & (MCHP_QMSPI_M_FDIV_MASK | MCHP_QMSPI_M_SIG_MASK);
224 cstim = regs->CSTM;
225 regs->MODE = MCHP_QMSPI_M_SRST;
226 regs->STS = MCHP_QMSPI_STS_RW1C_MASK;
227
228 MCHP_GIRQ_ENCLR(MCHP_QMSPI_GIRQ_NUM) = MCHP_QMSPI_GIRQ_VAL;
229 MCHP_GIRQ_SRC(MCHP_QMSPI_GIRQ_NUM) = MCHP_QMSPI_GIRQ_VAL;
230
231 regs->IFCTRL =
232 (MCHP_QMSPI_IFC_WP_OUT_HI | MCHP_QMSPI_IFC_WP_OUT_EN |
233 MCHP_QMSPI_IFC_HOLD_OUT_HI | MCHP_QMSPI_IFC_HOLD_OUT_EN);
234
235 for (n = 0; n < MCHP_SAF_NUM_GENERIC_DESCR; n++) {
236 regs->DESCR[MCHP_SAF_CM_EXIT_START_DESCR + n] =
237 hwcfg->generic_descr[n];
238 }
239
240 regs->IEN = MCHP_QMSPI_IEN_XFR_DONE;
241
242 qmode |= (MCHP_QMSPI_M_SAF_DMA_MODE_EN | MCHP_QMSPI_M_CS0 |
243 MCHP_QMSPI_M_ACTIVATE);
244
245 if (hwcfg->flags & MCHP_SAF_HW_CFG_FLAG_CPHA) {
246 qmode = (qmode & ~(MCHP_QMSPI_M_SIG_MASK)) |
247 ((hwcfg->qmspi_cpha << MCHP_QMSPI_M_SIG_POS) &
248 MCHP_QMSPI_M_SIG_MASK);
249 }
250
251 if (hwcfg->flags & MCHP_SAF_HW_CFG_FLAG_FREQ) {
252 qmode = (qmode & ~(MCHP_QMSPI_M_FDIV_MASK)) |
253 qmspi_freq_div(hwcfg->qmspi_freq_hz);
254 }
255
256 if (hwcfg->flags & MCHP_SAF_HW_CFG_FLAG_CSTM) {
257 cstim = hwcfg->qmspi_cs_timing;
258 }
259
260 regs->MODE = qmode;
261 regs->CSTM = cstim;
262
263 return 0;
264 }
265
266 /*
267 * Registers at offsets:
268 * SAF Poll timeout @ 0x194. Hard coded to 0x28000. Default value = 0.
269 * recommended value = 0x28000 32KHz clocks (5 seconds). b[17:0]
270 * SAF Poll interval @ 0x198. Hard coded to 0
271 * Default value = 0. Recommended = 0. b[15:0]
272 * SAF Suspend/Resume Interval @ 0x19c. Hard coded to 0x8
273 * Default value = 0x01. Min time erase/prog in 32KHz units.
274 * SAF Consecutive Read Timeout @ 0x1a0. Hard coded to 0x2. b[15:0]
275 * Units of MCLK. Recommend < 20us. b[19:0]
276 * SAF Suspend Check Delay @ 0x1ac. Not touched.
277 * Default = 0. Recommend = 20us. Units = MCLK. b[19:0]
278 */
saf_flash_timing_init(MCHP_SAF_HW_REGS * regs,const struct espi_saf_xec_config * cfg)279 static void saf_flash_timing_init(MCHP_SAF_HW_REGS *regs,
280 const struct espi_saf_xec_config *cfg)
281 {
282 LOG_DBG("%s\n", __func__);
283 regs->SAF_POLL_TMOUT = cfg->poll_timeout;
284 regs->SAF_POLL_INTRVL = cfg->poll_interval;
285 regs->SAF_SUS_RSM_INTRVL = cfg->sus_rsm_interval;
286 regs->SAF_CONSEC_RD_TMOUT = cfg->consec_rd_timeout;
287 regs->SAF_SUS_CHK_DLY = cfg->sus_chk_delay;
288 LOG_DBG("SAF_POLL_TMOUT %x\n", regs->SAF_POLL_TMOUT);
289 LOG_DBG("SAF_POLL_INTRVL %x\n", regs->SAF_POLL_INTRVL);
290 LOG_DBG("SAF_SUS_RSM_INTRVL %x\n", regs->SAF_SUS_RSM_INTRVL);
291 LOG_DBG("SAF_CONSEC_RD_TMOUT %x\n", regs->SAF_CONSEC_RD_TMOUT);
292 LOG_DBG("SAF_SUS_CHK_DLY %x\n", regs->SAF_SUS_CHK_DLY);
293 }
294
295 /*
296 * Disable DnX bypass feature.
297 */
saf_dnx_bypass_init(MCHP_SAF_HW_REGS * regs)298 static void saf_dnx_bypass_init(MCHP_SAF_HW_REGS *regs)
299 {
300 regs->SAF_DNX_PROT_BYP = 0;
301 regs->SAF_DNX_PROT_BYP = 0xffffffff;
302 }
303
304 /*
305 * Bitmap of flash erase size from 1KB up to 128KB.
306 * eSPI SAF specification requires 4KB erase support.
307 * MCHP SAF supports 4KB, 32KB, and 64KB.
308 * Only report 32KB and 64KB to Host if supported by both
309 * flash devices.
310 */
saf_init_erase_block_size(const struct espi_saf_cfg * cfg)311 static int saf_init_erase_block_size(const struct espi_saf_cfg *cfg)
312 {
313 struct espi_saf_flash_cfg *fcfg = cfg->flash_cfgs;
314 uint32_t opb = fcfg->opb;
315 uint8_t erase_bitmap = MCHP_ESPI_SERASE_SZ_4K;
316
317 LOG_DBG("%s\n", __func__);
318
319 if (cfg->nflash_devices > 1) {
320 fcfg++;
321 opb &= fcfg->opb;
322 }
323
324 if ((opb & MCHP_SAF_CS_OPB_ER0_MASK) == 0) {
325 /* One or both do not support 4KB erase! */
326 return -EINVAL;
327 }
328
329 if (opb & MCHP_SAF_CS_OPB_ER1_MASK) {
330 erase_bitmap |= MCHP_ESPI_SERASE_SZ_32K;
331 }
332
333 if (opb & MCHP_SAF_CS_OPB_ER2_MASK) {
334 erase_bitmap |= MCHP_ESPI_SERASE_SZ_64K;
335 }
336
337 ESPI_CAP_REGS->FC_SERBZ = erase_bitmap;
338
339 return 0;
340 }
341
342 /*
343 * Set the continuous mode prefix and 4-byte address mode bits
344 * based upon the flash configuration information.
345 * Updates:
346 * SAF Flash Config Poll2 Mask @ 0x1A4
347 * SAF Flash Config Special Mode @ 0x1B0
348 * SAF Flash Misc Config @ 0x38
349 */
saf_flash_misc_cfg(MCHP_SAF_HW_REGS * regs,uint8_t cs,const struct espi_saf_flash_cfg * fcfg)350 static void saf_flash_misc_cfg(MCHP_SAF_HW_REGS *regs, uint8_t cs,
351 const struct espi_saf_flash_cfg *fcfg)
352 {
353 uint32_t d, v;
354
355 d = regs->SAF_FL_CFG_MISC;
356
357 v = MCHP_SAF_FL_CFG_MISC_CS0_CPE;
358 if (cs) {
359 v = MCHP_SAF_FL_CFG_MISC_CS1_CPE;
360 }
361
362 /* Does this flash device require a prefix for continuous mode? */
363 if (fcfg->cont_prefix != 0) {
364 d |= v;
365 } else {
366 d &= ~v;
367 }
368
369 v = MCHP_SAF_FL_CFG_MISC_CS0_4BM;
370 if (cs) {
371 v = MCHP_SAF_FL_CFG_MISC_CS1_4BM;
372 }
373
374 /* Use 32-bit addressing for this flash device? */
375 if (fcfg->flags & MCHP_FLASH_FLAG_ADDR32) {
376 d |= v;
377 } else {
378 d &= ~v;
379 }
380
381 regs->SAF_FL_CFG_MISC = d;
382 LOG_DBG("%s SAF_FL_CFG_MISC: %x", __func__, d);
383 }
384
385 /*
386 * Program flash device specific SAF and QMSPI registers.
387 *
388 * CS0 OpA @ 0x4c or CS1 OpA @ 0x5C
389 * CS0 OpB @ 0x50 or CS1 OpB @ 0x60
390 * CS0 OpC @ 0x54 or CS1 OpC @ 0x64
391 * Poll 2 Mask @ 0x1a4
392 * Continuous Prefix @ 0x1b0
393 * CS0: QMSPI descriptors 0-5 or CS1 QMSPI descriptors 6-11
394 * CS0 Descrs @ 0x58 or CS1 Descrs @ 0x68
395 */
saf_flash_cfg(const struct device * dev,const struct espi_saf_flash_cfg * fcfg,uint8_t cs)396 static void saf_flash_cfg(const struct device *dev,
397 const struct espi_saf_flash_cfg *fcfg, uint8_t cs)
398 {
399 uint32_t d, did;
400 const struct espi_saf_xec_config *xcfg = DEV_CFG(dev);
401 MCHP_SAF_HW_REGS *regs = (MCHP_SAF_HW_REGS *)xcfg->saf_base_addr;
402 QMSPI_Type *qregs = (QMSPI_Type *)xcfg->qmspi_base_addr;
403
404 LOG_DBG("%s cs=%u", __func__, cs);
405
406 regs->SAF_CS_OP[cs].OPA = fcfg->opa;
407 regs->SAF_CS_OP[cs].OPB = fcfg->opb;
408 regs->SAF_CS_OP[cs].OPC = fcfg->opc;
409 regs->SAF_CS_OP[cs].OP_DESCR = (uint32_t)fcfg->cs_cfg_descr_ids;
410
411 did = MCHP_SAF_QMSPI_CS0_START_DESCR;
412 if (cs != 0) {
413 did = MCHP_SAF_QMSPI_CS1_START_DESCR;
414 }
415
416 for (size_t i = 0; i < MCHP_SAF_QMSPI_NUM_FLASH_DESCR; i++) {
417 d = fcfg->descr[i] & ~(MCHP_QMSPI_C_NEXT_DESCR_MASK);
418 d |= (((did + 1) << MCHP_QMSPI_C_NEXT_DESCR_POS) &
419 MCHP_QMSPI_C_NEXT_DESCR_MASK);
420 qregs->DESCR[did++] = d;
421 }
422
423 mchp_saf_poll2_mask_wr(regs, cs, fcfg->poll2_mask);
424 mchp_saf_cm_prefix_wr(regs, cs, fcfg->cont_prefix);
425 saf_flash_misc_cfg(regs, cs, fcfg);
426 }
427
428 static const uint32_t tag_map_dflt[MCHP_ESPI_SAF_TAGMAP_MAX] = {
429 MCHP_SAF_TAG_MAP0_DFLT, MCHP_SAF_TAG_MAP1_DFLT, MCHP_SAF_TAG_MAP2_DFLT
430 };
431
saf_tagmap_init(MCHP_SAF_HW_REGS * regs,const struct espi_saf_cfg * cfg)432 static void saf_tagmap_init(MCHP_SAF_HW_REGS *regs,
433 const struct espi_saf_cfg *cfg)
434 {
435 const struct espi_saf_hw_cfg *hwcfg = &cfg->hwcfg;
436
437 for (int i = 0; i < MCHP_ESPI_SAF_TAGMAP_MAX; i++) {
438 if (hwcfg->tag_map[i] & MCHP_SAF_HW_CFG_TAGMAP_USE) {
439 regs->SAF_TAG_MAP[i] = hwcfg->tag_map[i];
440 } else {
441 regs->SAF_TAG_MAP[i] = tag_map_dflt[i];
442 }
443 }
444
445 LOG_DBG("SAF TAG0 %x", regs->SAF_TAG_MAP[0]);
446 LOG_DBG("SAF TAG1 %x", regs->SAF_TAG_MAP[1]);
447 LOG_DBG("SAF TAG2 %x", regs->SAF_TAG_MAP[2]);
448 }
449
450 /*
451 * Configure SAF and QMSPI for SAF operation based upon the
452 * number and characteristics of local SPI flash devices.
453 * NOTE: SAF is configured but not activated. SAF should be
454 * activated only when eSPI master sends Flash Channel enable
455 * message with MAF/SAF select flag.
456 */
espi_saf_xec_configuration(const struct device * dev,const struct espi_saf_cfg * cfg)457 static int espi_saf_xec_configuration(const struct device *dev,
458 const struct espi_saf_cfg *cfg)
459 {
460 int ret = 0;
461 uint32_t totalsz = 0;
462 uint32_t u = 0;
463
464 LOG_DBG("%s", __func__);
465
466 if ((dev == NULL) || (cfg == NULL)) {
467 return -EINVAL;
468 }
469
470 const struct espi_saf_xec_config *xcfg = DEV_CFG(dev);
471 MCHP_SAF_HW_REGS *regs = (MCHP_SAF_HW_REGS *)xcfg->saf_base_addr;
472 const struct espi_saf_flash_cfg *fcfg = cfg->flash_cfgs;
473
474 if ((fcfg == NULL) || (cfg->nflash_devices == 0U) ||
475 (cfg->nflash_devices > MCHP_SAF_MAX_FLASH_DEVICES)) {
476 return -EINVAL;
477 }
478
479 if (regs->SAF_FL_CFG_MISC & MCHP_SAF_FL_CFG_MISC_SAF_EN) {
480 return -EAGAIN;
481 }
482
483 saf_qmspi_init(xcfg, cfg);
484
485 regs->SAF_CS0_CFG_P2M = 0;
486 regs->SAF_CS1_CFG_P2M = 0;
487
488 regs->SAF_FL_CFG_GEN_DESCR = MCHP_SAF_FL_CFG_GEN_DESCR_STD;
489
490 /* flash device connected to CS0 required */
491 totalsz = fcfg->flashsz;
492 regs->SAF_FL_CFG_THRH = totalsz;
493 saf_flash_cfg(dev, fcfg, 0);
494
495 /* optional second flash device connected to CS1 */
496 if (cfg->nflash_devices > 1) {
497 fcfg++;
498 totalsz += fcfg->flashsz;
499 }
500 /* Program CS1 configuration (same as CS0 if only one device) */
501 saf_flash_cfg(dev, fcfg, 1);
502
503 if (totalsz == 0) {
504 return -EAGAIN;
505 }
506
507 regs->SAF_FL_CFG_SIZE_LIM = totalsz - 1;
508
509 LOG_DBG("SAF_FL_CFG_THRH = %x SAF_FL_CFG_SIZE_LIM = %x",
510 regs->SAF_FL_CFG_THRH, regs->SAF_FL_CFG_SIZE_LIM);
511
512 saf_tagmap_init(regs, cfg);
513
514 saf_protection_regions_init(regs);
515
516 saf_dnx_bypass_init(regs);
517
518 saf_flash_timing_init(regs, xcfg);
519
520 ret = saf_init_erase_block_size(cfg);
521 if (ret != 0) {
522 LOG_ERR("SAF Config bad flash erase config");
523 return ret;
524 }
525
526 /* Default or expedited prefetch? */
527 u = MCHP_SAF_FL_CFG_MISC_PFOE_DFLT;
528 if (cfg->hwcfg.flags & MCHP_SAF_HW_CFG_FLAG_PFEXP) {
529 u = MCHP_SAF_FL_CFG_MISC_PFOE_EXP;
530 }
531
532 regs->SAF_FL_CFG_MISC =
533 (regs->SAF_FL_CFG_MISC & ~(MCHP_SAF_FL_CFG_MISC_PFOE_MASK)) | u;
534
535 /* enable prefetch ? */
536 if (cfg->hwcfg.flags & MCHP_SAF_HW_CFG_FLAG_PFEN) {
537 MCHP_SAF_COMM_MODE_REG |= MCHP_SAF_COMM_MODE_PF_EN;
538 } else {
539 MCHP_SAF_COMM_MODE_REG &= ~(MCHP_SAF_COMM_MODE_PF_EN);
540 }
541
542 LOG_DBG("%s SAF_FL_CFG_MISC: %x", __func__, regs->SAF_FL_CFG_MISC);
543 LOG_DBG("%s Aft MCHP_SAF_COMM_MODE_REG: %x", __func__,
544 MCHP_SAF_COMM_MODE_REG);
545
546 return 0;
547 }
548
espi_saf_xec_set_pr(const struct device * dev,const struct espi_saf_protection * pr)549 static int espi_saf_xec_set_pr(const struct device *dev,
550 const struct espi_saf_protection *pr)
551 {
552 if ((dev == NULL) || (pr == NULL)) {
553 return -EINVAL;
554 }
555
556 if (pr->nregions >= MCHP_ESPI_SAF_PR_MAX) {
557 return -EINVAL;
558 }
559
560 const struct espi_saf_xec_config *xcfg = DEV_CFG(dev);
561 MCHP_SAF_HW_REGS *regs = (MCHP_SAF_HW_REGS *)xcfg->saf_base_addr;
562
563 if (regs->SAF_FL_CFG_MISC & MCHP_SAF_FL_CFG_MISC_SAF_EN) {
564 return -EAGAIN;
565 }
566
567 const struct espi_saf_pr *preg = pr->pregions;
568 size_t n = pr->nregions;
569
570 while (n--) {
571 uint8_t regnum = preg->pr_num;
572
573 if (regnum >= MCHP_ESPI_SAF_PR_MAX) {
574 return -EINVAL;
575 }
576
577 /* NOTE: If previously locked writes have no effect */
578 if (preg->flags & MCHP_SAF_PR_FLAG_ENABLE) {
579 regs->SAF_PROT_RG[regnum].START = preg->start >> 12U;
580 regs->SAF_PROT_RG[regnum].LIMIT =
581 (preg->start + preg->size - 1U) >> 12U;
582 regs->SAF_PROT_RG[regnum].WEBM = preg->master_bm_we;
583 regs->SAF_PROT_RG[regnum].RDBM = preg->master_bm_rd;
584 } else {
585 regs->SAF_PROT_RG[regnum].START = 0x7FFFFU;
586 regs->SAF_PROT_RG[regnum].LIMIT = 0U;
587 regs->SAF_PROT_RG[regnum].WEBM = 0U;
588 regs->SAF_PROT_RG[regnum].RDBM = 0U;
589 }
590
591 if (preg->flags & MCHP_SAF_PR_FLAG_LOCK) {
592 regs->SAF_PROT_LOCK |= (1UL << regnum);
593 }
594
595 preg++;
596 }
597
598 return 0;
599 }
600
espi_saf_xec_channel_ready(const struct device * dev)601 static bool espi_saf_xec_channel_ready(const struct device *dev)
602 {
603 const struct espi_saf_xec_config *cfg = DEV_CFG(dev);
604 MCHP_SAF_HW_REGS *regs = (MCHP_SAF_HW_REGS *)cfg->saf_base_addr;
605
606 if (regs->SAF_FL_CFG_MISC & MCHP_SAF_FL_CFG_MISC_SAF_EN) {
607 return true;
608 }
609
610 return false;
611 }
612
613 /*
614 * MCHP SAF hardware supports a range of flash block erase
615 * sizes from 1KB to 128KB. The eSPI Host specification requires
616 * 4KB must be supported. The MCHP SAF QMSPI HW interface only
617 * supported three erase sizes. Most SPI flash devices chosen for
618 * SAF support 4KB, 32KB, and 64KB.
619 * Get flash erase sizes driver has configured from eSPI capabilities
620 * registers. We assume driver flash tables have opcodes to match
621 * capabilities configuration.
622 * Check requested erase size is supported.
623 */
624 struct erase_size_encoding {
625 uint8_t hwbitpos;
626 uint8_t encoding;
627 };
628
629 static const struct erase_size_encoding ersz_enc[] = {
630 { MCHP_ESPI_SERASE_SZ_4K_BITPOS, 0 },
631 { MCHP_ESPI_SERASE_SZ_32K_BITPOS, 1 },
632 { MCHP_ESPI_SERASE_SZ_64K_BITPOS, 2 }
633 };
634
635 #define SAF_ERASE_ENCODING_MAX_ENTRY \
636 (sizeof(ersz_enc) / sizeof(struct erase_size_encoding))
637
get_erase_size_encoding(uint32_t erase_size)638 static uint32_t get_erase_size_encoding(uint32_t erase_size)
639 {
640 uint8_t supsz = ESPI_CAP_REGS->FC_SERBZ;
641
642 LOG_DBG("%s\n", __func__);
643 for (int i = 0; i < SAF_ERASE_ENCODING_MAX_ENTRY; i++) {
644 uint32_t sz = MCHP_ESPI_SERASE_SZ(ersz_enc[i].hwbitpos);
645
646 if ((sz == erase_size) &&
647 (supsz & (1 << ersz_enc[i].hwbitpos))) {
648 return ersz_enc[i].encoding;
649 }
650 }
651
652 return 0xffffffffU;
653 }
654
check_ecp_access_size(uint32_t reqlen)655 static int check_ecp_access_size(uint32_t reqlen)
656 {
657 if ((reqlen < MCHP_SAF_ECP_CMD_RW_LEN_MIN) ||
658 (reqlen > MCHP_SAF_ECP_CMD_RW_LEN_MAX)) {
659 return -EAGAIN;
660 }
661
662 return 0;
663 }
664
665 /*
666 * EC access (read/erase/write) to SAF atttached flash array
667 * cmd 0 = read
668 * 1 = write
669 * 2 = erase
670 */
saf_ecp_access(const struct device * dev,struct espi_saf_packet * pckt,uint8_t cmd)671 static int saf_ecp_access(const struct device *dev,
672 struct espi_saf_packet *pckt, uint8_t cmd)
673 {
674 uint32_t err_mask, n;
675 int rc, counter;
676 struct espi_saf_xec_data *xdat = DEV_DATA(dev);
677 const struct espi_saf_xec_config *cfg = DEV_CFG(dev);
678 MCHP_SAF_HW_REGS *regs = (MCHP_SAF_HW_REGS *)cfg->saf_base_addr;
679
680 counter = 0;
681 err_mask = MCHP_SAF_ECP_STS_ERR_MASK;
682
683 LOG_DBG("%s", __func__);
684
685 if (!(regs->SAF_FL_CFG_MISC & MCHP_SAF_FL_CFG_MISC_SAF_EN)) {
686 LOG_ERR("SAF is disabled");
687 return -EIO;
688 }
689
690 if (regs->SAF_ECP_BUSY & MCHP_SAF_ECP_BUSY) {
691 LOG_ERR("SAF EC Portal is busy");
692 return -EBUSY;
693 }
694
695 if ((cmd == MCHP_SAF_ECP_CMD_CTYPE_READ0) ||
696 (cmd == MCHP_SAF_ECP_CMD_CTYPE_WRITE0)) {
697 rc = check_ecp_access_size(pckt->len);
698 if (rc) {
699 LOG_ERR("SAF EC Portal size out of bounds");
700 return rc;
701 }
702
703 if (cmd == MCHP_SAF_ECP_CMD_CTYPE_WRITE0) {
704 memcpy(slave_mem, pckt->buf, pckt->len);
705 }
706
707 n = pckt->len;
708 } else if (cmd == MCHP_SAF_ECP_CMD_CTYPE_ERASE0) {
709 n = get_erase_size_encoding(pckt->len);
710 if (n == 0xffffffff) {
711 LOG_ERR("SAF EC Portal unsupported erase size");
712 return -EAGAIN;
713 }
714 } else {
715 LOG_ERR("SAF EC Portal bad cmd");
716 return -EAGAIN;
717 }
718
719 LOG_DBG("%s params val done", __func__);
720
721 k_sem_take(&xdat->ecp_lock, K_FOREVER);
722
723 regs->SAF_ECP_INTEN = 0;
724 regs->SAF_ECP_STATUS = 0xffffffff;
725
726 /*
727 * TODO - Force SAF Done interrupt disabled until we have support
728 * from eSPI driver.
729 */
730 MCHP_GIRQ_ENCLR(MCHP_SAF_GIRQ) = MCHP_SAF_GIRQ_ECP_DONE_BIT;
731 MCHP_GIRQ_SRC(MCHP_SAF_GIRQ) = MCHP_SAF_GIRQ_ECP_DONE_BIT;
732
733 regs->SAF_ECP_FLAR = pckt->flash_addr;
734 regs->SAF_ECP_BFAR = (uint32_t)&slave_mem[0];
735
736 regs->SAF_ECP_CMD =
737 MCHP_SAF_ECP_CMD_PUT_FLASH_NP |
738 ((uint32_t)cmd << MCHP_SAF_ECP_CMD_CTYPE_POS) |
739 ((n << MCHP_SAF_ECP_CMD_LEN_POS) & MCHP_SAF_ECP_CMD_LEN_MASK);
740
741 /* TODO when interrupts are available enable here */
742 regs->SAF_ECP_START = MCHP_SAF_ECP_START;
743
744 /* TODO
745 * ISR is in eSPI driver. Use polling until eSPI driver has been
746 * modified to provide callback for GIRQ19 SAF ECP Done.
747 */
748 rc = 0;
749 xdat->hwstatus = regs->SAF_ECP_STATUS;
750 while (!(xdat->hwstatus & MCHP_SAF_ECP_STS_DONE)) {
751 rc = xec_saf_spin_yield(&counter);
752 if (rc < 0) {
753 goto ecp_exit;
754 }
755 xdat->hwstatus = regs->SAF_ECP_STATUS;
756 }
757
758 /* clear hardware status and check for errors */
759 regs->SAF_ECP_STATUS = xdat->hwstatus;
760 if (xdat->hwstatus & MCHP_SAF_ECP_STS_ERR_MASK) {
761 rc = -EIO;
762 goto ecp_exit;
763 }
764
765 if (cmd == MCHP_SAF_ECP_CMD_CTYPE_READ0) {
766 memcpy(pckt->buf, slave_mem, pckt->len);
767 }
768
769 ecp_exit:
770 k_sem_give(&xdat->ecp_lock);
771
772 return rc;
773 }
774
775 /* Flash read using SAF EC Portal */
saf_xec_flash_read(const struct device * dev,struct espi_saf_packet * pckt)776 static int saf_xec_flash_read(const struct device *dev,
777 struct espi_saf_packet *pckt)
778 {
779 LOG_DBG("%s", __func__);
780 return saf_ecp_access(dev, pckt, MCHP_SAF_ECP_CMD_CTYPE_READ0);
781 }
782
783 /* Flash write using SAF EC Portal */
saf_xec_flash_write(const struct device * dev,struct espi_saf_packet * pckt)784 static int saf_xec_flash_write(const struct device *dev,
785 struct espi_saf_packet *pckt)
786 {
787 return saf_ecp_access(dev, pckt, MCHP_SAF_ECP_CMD_CTYPE_WRITE0);
788 }
789
790 /* Flash erase using SAF EC Portal */
saf_xec_flash_erase(const struct device * dev,struct espi_saf_packet * pckt)791 static int saf_xec_flash_erase(const struct device *dev,
792 struct espi_saf_packet *pckt)
793 {
794 return saf_ecp_access(dev, pckt, MCHP_SAF_ECP_CMD_CTYPE_ERASE0);
795 }
796
espi_saf_xec_manage_callback(const struct device * dev,struct espi_callback * callback,bool set)797 static int espi_saf_xec_manage_callback(const struct device *dev,
798 struct espi_callback *callback,
799 bool set)
800 {
801 struct espi_saf_xec_data *data = DEV_DATA(dev);
802
803 return espi_manage_callback(&data->callbacks, callback, set);
804 }
805
espi_saf_xec_activate(const struct device * dev)806 static int espi_saf_xec_activate(const struct device *dev)
807 {
808 const struct espi_saf_xec_config *cfg;
809 MCHP_SAF_HW_REGS *regs;
810
811 if (dev == NULL) {
812 return -EINVAL;
813 }
814
815 cfg = DEV_CFG(dev);
816 regs = (MCHP_SAF_HW_REGS *)cfg->saf_base_addr;
817
818 regs->SAF_FL_CFG_MISC |= MCHP_SAF_FL_CFG_MISC_SAF_EN;
819
820 return 0;
821 }
822
823 static int espi_saf_xec_init(const struct device *dev);
824
825 static const struct espi_saf_driver_api espi_saf_xec_driver_api = {
826 .config = espi_saf_xec_configuration,
827 .set_protection_regions = espi_saf_xec_set_pr,
828 .activate = espi_saf_xec_activate,
829 .get_channel_status = espi_saf_xec_channel_ready,
830 .flash_read = saf_xec_flash_read,
831 .flash_write = saf_xec_flash_write,
832 .flash_erase = saf_xec_flash_erase,
833 .manage_callback = espi_saf_xec_manage_callback,
834 };
835
836 static struct espi_saf_xec_data espi_saf_xec_data;
837
838 static const struct espi_saf_xec_config espi_saf_xec_config = {
839 .saf_base_addr = DT_INST_REG_ADDR_BY_IDX(0, 0),
840 .qmspi_base_addr = DT_INST_REG_ADDR_BY_IDX(0, 1),
841 .saf_comm_base_addr = DT_INST_REG_ADDR_BY_IDX(0, 2),
842 .poll_timeout = DT_INST_PROP_OR(inst, poll_timeout,
843 MCHP_SAF_FLASH_POLL_TIMEOUT),
844 .consec_rd_timeout = DT_INST_PROP_OR(
845 inst, consec_rd_timeout, MCHP_SAF_FLASH_CONSEC_READ_TIMEOUT),
846 .sus_chk_delay = DT_INST_PROP_OR(inst, sus_chk_delay,
847 MCHP_SAF_FLASH_SUS_CHK_DELAY),
848 .sus_rsm_interval = DT_INST_PROP_OR(inst, sus_rsm_interval,
849 MCHP_SAF_FLASH_SUS_RSM_INTERVAL),
850 .poll_interval = DT_INST_PROP_OR(inst, poll_interval,
851 MCHP_SAF_FLASH_POLL_INTERVAL),
852 };
853
854 DEVICE_DT_INST_DEFINE(0, &espi_saf_xec_init, NULL,
855 &espi_saf_xec_data, &espi_saf_xec_config, POST_KERNEL,
856 CONFIG_ESPI_SAF_INIT_PRIORITY, &espi_saf_xec_driver_api);
857
espi_saf_xec_init(const struct device * dev)858 static int espi_saf_xec_init(const struct device *dev)
859 {
860 struct espi_saf_xec_data *data = DEV_DATA(dev);
861
862 /* ungate SAF clocks by disabling PCR sleep enable */
863 mchp_pcr_periph_slp_ctrl(PCR_ESPI_SAF, MCHP_PCR_SLEEP_DIS);
864
865 /* reset the SAF block */
866 mchp_pcr_periph_reset(PCR_ESPI_SAF);
867
868 /* Configure the channels and its capabilities based on build config */
869 ESPI_CAP_REGS->GLB_CAP0 |= MCHP_ESPI_GBL_CAP0_FC_SUPP;
870 ESPI_CAP_REGS->FC_CAP &= ~(MCHP_ESPI_FC_CAP_SHARE_MASK);
871 ESPI_CAP_REGS->FC_CAP |= MCHP_ESPI_FC_CAP_SHARE_MAF_SAF;
872
873 k_sem_init(&data->ecp_lock, 1, 1);
874
875 return 0;
876 }
877
