1 /* 2 * Copyright (c) 2020 Teslabs Engineering S.L. 3 * Copyright (c) 2021 Krivorot Oleg <krivorot.oleg@gmail.com> 4 * 5 * SPDX-License-Identifier: Apache-2.0 6 */ 7 #ifndef ZEPHYR_DRIVERS_DISPLAY_DISPLAY_ILI9341_H_ 8 #define ZEPHYR_DRIVERS_DISPLAY_DISPLAY_ILI9341_H_ 9 10 #include <device.h> 11 12 /* Commands/registers. */ 13 #define ILI9341_GAMSET 0x26 14 #define ILI9341_FRMCTR1 0xB1 15 #define ILI9341_DISCTRL 0xB6 16 #define ILI9341_ETMOD 0xB7 17 #define ILI9341_PWCTRL1 0xC0 18 #define ILI9341_PWCTRL2 0xC1 19 #define ILI9341_VMCTRL1 0xC5 20 #define ILI9341_VMCTRL2 0xC7 21 #define ILI9341_PWCTRLA 0xCB 22 #define ILI9341_PWCTRLB 0xCF 23 #define ILI9341_PGAMCTRL 0xE0 24 #define ILI9341_NGAMCTRL 0xE1 25 #define ILI9341_TIMCTRLA 0xE8 26 #define ILI9341_TIMCTRLB 0xEA 27 #define ILI9341_PWSEQCTRL 0xED 28 #define ILI9341_ENABLE3G 0xF2 29 #define ILI9341_PUMPRATIOCTRL 0xF7 30 31 /* Commands/registers length. */ 32 #define ILI9341_GAMSET_LEN 1U 33 #define ILI9341_FRMCTR1_LEN 2U 34 #define ILI9341_DISCTRL_LEN 3U 35 #define ILI9341_PWCTRL1_LEN 1U 36 #define ILI9341_PWCTRL2_LEN 1U 37 #define ILI9341_VMCTRL1_LEN 2U 38 #define ILI9341_VMCTRL2_LEN 1U 39 #define ILI9341_PGAMCTRL_LEN 15U 40 #define ILI9341_NGAMCTRL_LEN 15U 41 #define ILI9341_PWCTRLA_LEN 5U 42 #define ILI9341_PWCTRLB_LEN 3U 43 #define ILI9341_PWSEQCTRL_LEN 4U 44 #define ILI9341_TIMCTRLA_LEN 3U 45 #define ILI9341_TIMCTRLB_LEN 2U 46 #define ILI9341_PUMPRATIOCTRL_LEN 1U 47 #define ILI9341_ENABLE3G_LEN 1U 48 #define ILI9341_ETMOD_LEN 1U 49 50 /** X resolution (pixels). */ 51 #define ILI9341_X_RES 240U 52 /** Y resolution (pixels). */ 53 #define ILI9341_Y_RES 320U 54 55 /** ILI9341 registers to be initialized. */ 56 struct ili9341_regs { 57 uint8_t gamset[ILI9341_GAMSET_LEN]; 58 uint8_t frmctr1[ILI9341_FRMCTR1_LEN]; 59 uint8_t disctrl[ILI9341_DISCTRL_LEN]; 60 uint8_t pwctrl1[ILI9341_PWCTRL1_LEN]; 61 uint8_t pwctrl2[ILI9341_PWCTRL2_LEN]; 62 uint8_t vmctrl1[ILI9341_VMCTRL1_LEN]; 63 uint8_t vmctrl2[ILI9341_VMCTRL2_LEN]; 64 uint8_t pgamctrl[ILI9341_PGAMCTRL_LEN]; 65 uint8_t ngamctrl[ILI9341_NGAMCTRL_LEN]; 66 uint8_t pwctrla[ILI9341_PWCTRLA_LEN]; 67 uint8_t pwctrlb[ILI9341_PWCTRLB_LEN]; 68 uint8_t pwseqctrl[ILI9341_PWSEQCTRL_LEN]; 69 uint8_t timctrla[ILI9341_TIMCTRLA_LEN]; 70 uint8_t timctrlb[ILI9341_TIMCTRLB_LEN]; 71 uint8_t pumpratioctrl[ILI9341_PUMPRATIOCTRL_LEN]; 72 uint8_t enable3g[ILI9341_ENABLE3G_LEN]; 73 uint8_t etmod[ILI9341_ETMOD_LEN]; 74 }; 75 76 /* Initializer macro for ILI9341 registers. */ 77 #define ILI9341_REGS_INIT(n) \ 78 BUILD_ASSERT(DT_PROP_LEN(DT_INST(n, ilitek_ili9341), gamset) == ILI9341_GAMSET_LEN, \ 79 "ili9341: Error length gamma set (GAMSET) register"); \ 80 BUILD_ASSERT(DT_PROP_LEN(DT_INST(n, ilitek_ili9341), frmctr1) == ILI9341_FRMCTR1_LEN, \ 81 "ili9341: Error length frame rate control (FRMCTR1) register"); \ 82 BUILD_ASSERT(DT_PROP_LEN(DT_INST(n, ilitek_ili9341), disctrl) == ILI9341_DISCTRL_LEN, \ 83 "ili9341: Error length display function control (DISCTRL) register"); \ 84 BUILD_ASSERT(DT_PROP_LEN(DT_INST(n, ilitek_ili9341), pwctrl1) == ILI9341_PWCTRL1_LEN, \ 85 "ili9341: Error length power control 1 (PWCTRL1) register"); \ 86 BUILD_ASSERT(DT_PROP_LEN(DT_INST(n, ilitek_ili9341), pwctrl2) == ILI9341_PWCTRL2_LEN, \ 87 "ili9341: Error length power control 2 (PWCTRL2) register"); \ 88 BUILD_ASSERT(DT_PROP_LEN(DT_INST(n, ilitek_ili9341), vmctrl1) == ILI9341_VMCTRL1_LEN, \ 89 "ili9341: Error length VCOM control 1 (VMCTRL1) register"); \ 90 BUILD_ASSERT(DT_PROP_LEN(DT_INST(n, ilitek_ili9341), vmctrl2) == ILI9341_VMCTRL2_LEN, \ 91 "ili9341: Error length VCOM control 2 (VMCTRL2) register"); \ 92 BUILD_ASSERT(DT_PROP_LEN(DT_INST(n, ilitek_ili9341), pgamctrl) == ILI9341_PGAMCTRL_LEN, \ 93 "ili9341: Error length positive gamma correction (PGAMCTRL) register"); \ 94 BUILD_ASSERT(DT_PROP_LEN(DT_INST(n, ilitek_ili9341), ngamctrl) == ILI9341_NGAMCTRL_LEN, \ 95 "ili9341: Error length negative gamma correction (NGAMCTRL) register"); \ 96 BUILD_ASSERT(DT_PROP_LEN(DT_INST(n, ilitek_ili9341), pwctrla) == ILI9341_PWCTRLA_LEN, \ 97 "ili9341: Error length power control A (PWCTRLA) register"); \ 98 BUILD_ASSERT(DT_PROP_LEN(DT_INST(n, ilitek_ili9341), pwctrlb) == ILI9341_PWCTRLB_LEN, \ 99 "ili9341: Error length power control B (PWCTRLB) register"); \ 100 BUILD_ASSERT(DT_PROP_LEN(DT_INST(n, ilitek_ili9341), pwseqctrl) == ILI9341_PWSEQCTRL_LEN, \ 101 "ili9341: Error length power on sequence control (PWSEQCTRL) register"); \ 102 BUILD_ASSERT(DT_PROP_LEN(DT_INST(n, ilitek_ili9341), timctrla) == ILI9341_TIMCTRLA_LEN, \ 103 "ili9341: Error length driver timing control A (TIMCTRLA) register"); \ 104 BUILD_ASSERT(DT_PROP_LEN(DT_INST(n, ilitek_ili9341), timctrlb) == ILI9341_TIMCTRLB_LEN, \ 105 "ili9341: Error length driver timing control B (TIMCTRLB) register"); \ 106 BUILD_ASSERT(DT_PROP_LEN(DT_INST(n, ilitek_ili9341), pumpratioctrl) == \ 107 ILI9341_PUMPRATIOCTRL_LEN, \ 108 "ili9341: Error length Pump ratio control (PUMPRATIOCTRL) register"); \ 109 BUILD_ASSERT(DT_PROP_LEN(DT_INST(n, ilitek_ili9341), enable3g) == ILI9341_ENABLE3G_LEN, \ 110 "ili9341: Error length enable 3G (ENABLE3G) register"); \ 111 BUILD_ASSERT(DT_PROP_LEN(DT_INST(n, ilitek_ili9341), etmod) == ILI9341_ETMOD_LEN, \ 112 "ili9341: Error length entry Mode Set (ETMOD) register"); \ 113 static const struct ili9341_regs ili9xxx_regs_##n = { \ 114 .gamset = DT_PROP(DT_INST(n, ilitek_ili9341), gamset), \ 115 .frmctr1 = DT_PROP(DT_INST(n, ilitek_ili9341), frmctr1), \ 116 .disctrl = DT_PROP(DT_INST(n, ilitek_ili9341), disctrl), \ 117 .pwctrl1 = DT_PROP(DT_INST(n, ilitek_ili9341), pwctrl1), \ 118 .pwctrl2 = DT_PROP(DT_INST(n, ilitek_ili9341), pwctrl2), \ 119 .vmctrl1 = DT_PROP(DT_INST(n, ilitek_ili9341), vmctrl1), \ 120 .vmctrl2 = DT_PROP(DT_INST(n, ilitek_ili9341), vmctrl2), \ 121 .pgamctrl = DT_PROP(DT_INST(n, ilitek_ili9341), pgamctrl), \ 122 .ngamctrl = DT_PROP(DT_INST(n, ilitek_ili9341), ngamctrl), \ 123 .pwctrla = DT_PROP(DT_INST(n, ilitek_ili9341), pwctrla), \ 124 .pwctrlb = DT_PROP(DT_INST(n, ilitek_ili9341), pwctrlb), \ 125 .pwseqctrl = DT_PROP(DT_INST(n, ilitek_ili9341), pwseqctrl), \ 126 .timctrla = DT_PROP(DT_INST(n, ilitek_ili9341), timctrla), \ 127 .timctrlb = DT_PROP(DT_INST(n, ilitek_ili9341), timctrlb), \ 128 .pumpratioctrl = DT_PROP(DT_INST(n, ilitek_ili9341), pumpratioctrl), \ 129 .enable3g = DT_PROP(DT_INST(n, ilitek_ili9341), enable3g), \ 130 .etmod = DT_PROP(DT_INST(n, ilitek_ili9341), etmod), \ 131 } 132 133 /** 134 * @brief Initialize ILI9341 registers with DT values. 135 * 136 * @param dev ILI9341 device instance 137 * @return 0 on success, errno otherwise. 138 */ 139 int ili9341_regs_init(const struct device *dev); 140 141 #endif /* ZEPHYR_DRIVERS_DISPLAY_DISPLAY_ILI9341_H_ */ 142
