1 /*
2  * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 #include <drivers/counter.h>
7 #include <hal/nrf_timer.h>
8 #include <sys/atomic.h>
9 
10 #define LOG_LEVEL CONFIG_COUNTER_LOG_LEVEL
11 #define LOG_MODULE_NAME counter_timer
12 #include <logging/log.h>
13 LOG_MODULE_REGISTER(LOG_MODULE_NAME, LOG_LEVEL);
14 
15 #define TIMER_CLOCK 16000000
16 
17 #define CC_TO_ID(cc_num) (cc_num - 2)
18 
19 #define ID_TO_CC(idx) (nrf_timer_cc_channel_t)(idx + 2)
20 
21 #define TOP_CH NRF_TIMER_CC_CHANNEL0
22 #define COUNTER_TOP_EVT NRF_TIMER_EVENT_COMPARE0
23 #define COUNTER_TOP_INT_MASK NRF_TIMER_INT_COMPARE0_MASK
24 
25 #define COUNTER_OVERFLOW_SHORT NRF_TIMER_SHORT_COMPARE0_CLEAR_MASK
26 #define COUNTER_READ_CC NRF_TIMER_CC_CHANNEL1
27 
28 struct counter_nrfx_data {
29 	counter_top_callback_t top_cb;
30 	void *top_user_data;
31 	uint32_t guard_period;
32 	atomic_t cc_int_pending;
33 };
34 
35 struct counter_nrfx_ch_data {
36 	counter_alarm_callback_t callback;
37 	void *user_data;
38 };
39 
40 struct counter_nrfx_config {
41 	struct counter_config_info info;
42 	struct counter_nrfx_ch_data *ch_data;
43 	NRF_TIMER_Type *timer;
44 	LOG_INSTANCE_PTR_DECLARE(log);
45 };
46 
47 struct counter_timer_config {
48 	nrf_timer_bit_width_t bit_width;
49 	nrf_timer_mode_t mode;
50 	nrf_timer_frequency_t freq;
51 };
52 
get_dev_data(const struct device * dev)53 static inline struct counter_nrfx_data *get_dev_data(const struct device *dev)
54 {
55 	return dev->data;
56 }
57 
get_nrfx_config(const struct device * dev)58 static inline const struct counter_nrfx_config *get_nrfx_config(const struct device *dev)
59 {
60 	return CONTAINER_OF(dev->config,
61 				struct counter_nrfx_config, info);
62 }
63 
start(const struct device * dev)64 static int start(const struct device *dev)
65 {
66 	nrf_timer_task_trigger(get_nrfx_config(dev)->timer,
67 			       NRF_TIMER_TASK_START);
68 
69 	return 0;
70 }
71 
stop(const struct device * dev)72 static int stop(const struct device *dev)
73 {
74 	nrf_timer_task_trigger(get_nrfx_config(dev)->timer,
75 				NRF_TIMER_TASK_SHUTDOWN);
76 
77 	return 0;
78 }
79 
get_top_value(const struct device * dev)80 static uint32_t get_top_value(const struct device *dev)
81 {
82 	return nrf_timer_cc_get(get_nrfx_config(dev)->timer, TOP_CH);
83 }
84 
read(const struct device * dev)85 static uint32_t read(const struct device *dev)
86 {
87 	NRF_TIMER_Type *timer = get_nrfx_config(dev)->timer;
88 
89 	nrf_timer_task_trigger(timer,
90 			       nrf_timer_capture_task_get(COUNTER_READ_CC));
91 
92 	return nrf_timer_cc_get(timer, COUNTER_READ_CC);
93 }
94 
get_value(const struct device * dev,uint32_t * ticks)95 static int get_value(const struct device *dev, uint32_t *ticks)
96 {
97 	*ticks = read(dev);
98 	return 0;
99 }
100 
101 /* Return true if value equals 2^n - 1 */
is_bit_mask(uint32_t val)102 static inline bool is_bit_mask(uint32_t val)
103 {
104 	return !(val & (val + 1));
105 }
106 
ticks_add(uint32_t val1,uint32_t val2,uint32_t top)107 static uint32_t ticks_add(uint32_t val1, uint32_t val2, uint32_t top)
108 {
109 	uint32_t to_top;
110 
111 	if (likely(is_bit_mask(top))) {
112 		return (val1 + val2) & top;
113 	}
114 
115 	to_top = top - val1;
116 
117 	return (val2 <= to_top) ? val1 + val2 : val2 - to_top;
118 }
119 
ticks_sub(uint32_t val,uint32_t old,uint32_t top)120 static uint32_t ticks_sub(uint32_t val, uint32_t old, uint32_t top)
121 {
122 	if (likely(is_bit_mask(top))) {
123 		return (val - old) & top;
124 	}
125 
126 	/* if top is not 2^n-1 */
127 	return (val >= old) ? (val - old) : val + top + 1 - old;
128 }
129 
set_cc_int_pending(const struct device * dev,uint8_t chan)130 static void set_cc_int_pending(const struct device *dev, uint8_t chan)
131 {
132 	atomic_or(&get_dev_data(dev)->cc_int_pending, BIT(chan));
133 	NRFX_IRQ_PENDING_SET(NRFX_IRQ_NUMBER_GET(get_nrfx_config(dev)->timer));
134 }
135 
set_cc(const struct device * dev,uint8_t id,uint32_t val,uint32_t flags)136 static int set_cc(const struct device *dev, uint8_t id, uint32_t val,
137 		  uint32_t flags)
138 {
139 	__ASSERT_NO_MSG(get_dev_data(dev)->guard_period < get_top_value(dev));
140 	bool absolute = flags & COUNTER_ALARM_CFG_ABSOLUTE;
141 	bool irq_on_late;
142 	NRF_TIMER_Type  *reg = get_nrfx_config(dev)->timer;
143 	uint8_t chan = ID_TO_CC(id);
144 	nrf_timer_event_t evt = nrf_timer_compare_event_get(chan);
145 	uint32_t top = get_top_value(dev);
146 	int err = 0;
147 	uint32_t prev_val;
148 	uint32_t now;
149 	uint32_t diff;
150 	uint32_t max_rel_val;
151 
152 	__ASSERT(nrf_timer_int_enable_check(reg,
153 				nrf_timer_compare_int_get(chan)) == 0,
154 				"Expected that CC interrupt is disabled.");
155 
156 	/* First take care of a risk of an event coming from CC being set to
157 	 * next tick. Reconfigure CC to future (now tick is the furtherest
158 	 * future).
159 	 */
160 	now = read(dev);
161 	prev_val = nrf_timer_cc_get(reg, chan);
162 	nrf_timer_cc_set(reg, chan, now);
163 	nrf_timer_event_clear(reg, evt);
164 
165 	if (absolute) {
166 		max_rel_val = top - get_dev_data(dev)->guard_period;
167 		irq_on_late = flags & COUNTER_ALARM_CFG_EXPIRE_WHEN_LATE;
168 	} else {
169 		/* If relative value is smaller than half of the counter range
170 		 * it is assumed that there is a risk of setting value too late
171 		 * and late detection algorithm must be applied. When late
172 		 * setting is detected, interrupt shall be triggered for
173 		 * immediate expiration of the timer. Detection is performed
174 		 * by limiting relative distance between CC and counter.
175 		 *
176 		 * Note that half of counter range is an arbitrary value.
177 		 */
178 		irq_on_late = val < (top / 2);
179 		/* limit max to detect short relative being set too late. */
180 		max_rel_val = irq_on_late ? top / 2 : top;
181 		val = ticks_add(now, val, top);
182 	}
183 
184 	nrf_timer_cc_set(reg, chan, val);
185 
186 	/* decrement value to detect also case when val == read(dev). Otherwise,
187 	 * condition would need to include comparing diff against 0.
188 	 */
189 	diff = ticks_sub(val - 1, read(dev), top);
190 	if (diff > max_rel_val) {
191 		if (absolute) {
192 			err = -ETIME;
193 		}
194 
195 		/* Interrupt is triggered always for relative alarm and
196 		 * for absolute depending on the flag.
197 		 */
198 		if (irq_on_late) {
199 			set_cc_int_pending(dev, chan);
200 		} else {
201 			get_nrfx_config(dev)->ch_data[id].callback = NULL;
202 		}
203 	} else {
204 		nrf_timer_int_enable(reg, nrf_timer_compare_int_get(chan));
205 	}
206 
207 	return err;
208 }
209 
set_alarm(const struct device * dev,uint8_t chan,const struct counter_alarm_cfg * alarm_cfg)210 static int set_alarm(const struct device *dev, uint8_t chan,
211 			const struct counter_alarm_cfg *alarm_cfg)
212 {
213 	const struct counter_nrfx_config *nrfx_config = get_nrfx_config(dev);
214 	struct counter_nrfx_ch_data *chdata = &nrfx_config->ch_data[chan];
215 
216 	if (alarm_cfg->ticks >  get_top_value(dev)) {
217 		return -EINVAL;
218 	}
219 
220 	if (chdata->callback) {
221 		return -EBUSY;
222 	}
223 
224 	chdata->callback = alarm_cfg->callback;
225 	chdata->user_data = alarm_cfg->user_data;
226 
227 	return set_cc(dev, chan, alarm_cfg->ticks, alarm_cfg->flags);
228 }
229 
cancel_alarm(const struct device * dev,uint8_t chan_id)230 static int cancel_alarm(const struct device *dev, uint8_t chan_id)
231 {
232 	const struct counter_nrfx_config *config = get_nrfx_config(dev);
233 	uint32_t int_mask =  nrf_timer_compare_int_get(ID_TO_CC(chan_id));
234 
235 	nrf_timer_int_disable(config->timer, int_mask);
236 	config->ch_data[chan_id].callback = NULL;
237 
238 	return 0;
239 }
240 
set_top_value(const struct device * dev,const struct counter_top_cfg * cfg)241 static int set_top_value(const struct device *dev,
242 			 const struct counter_top_cfg *cfg)
243 {
244 	const struct counter_nrfx_config *nrfx_config = get_nrfx_config(dev);
245 	NRF_TIMER_Type *timer = get_nrfx_config(dev)->timer;
246 	struct counter_nrfx_data *data = get_dev_data(dev);
247 	int err = 0;
248 
249 	for (int i = 0; i < counter_get_num_of_channels(dev); i++) {
250 		/* Overflow can be changed only when all alarms are
251 		 * disables.
252 		 */
253 		if (nrfx_config->ch_data[i].callback) {
254 			return -EBUSY;
255 		}
256 	}
257 
258 	nrf_timer_int_disable(timer, COUNTER_TOP_INT_MASK);
259 	nrf_timer_cc_set(timer, TOP_CH, cfg->ticks);
260 	nrf_timer_shorts_enable(timer, COUNTER_OVERFLOW_SHORT);
261 
262 	data->top_cb = cfg->callback;
263 	data->top_user_data = cfg->user_data;
264 
265 	if (!(cfg->flags & COUNTER_TOP_CFG_DONT_RESET)) {
266 		nrf_timer_task_trigger(timer, NRF_TIMER_TASK_CLEAR);
267 	} else if (read(dev) >= cfg->ticks) {
268 		err = -ETIME;
269 		if (cfg->flags & COUNTER_TOP_CFG_RESET_WHEN_LATE) {
270 			nrf_timer_task_trigger(timer, NRF_TIMER_TASK_CLEAR);
271 		}
272 	}
273 
274 	if (cfg->callback) {
275 		nrf_timer_int_enable(timer, COUNTER_TOP_INT_MASK);
276 	}
277 
278 	return err;
279 }
280 
get_pending_int(const struct device * dev)281 static uint32_t get_pending_int(const struct device *dev)
282 {
283 	return 0;
284 }
285 
init_timer(const struct device * dev,const struct counter_timer_config * config)286 static int init_timer(const struct device *dev,
287 		      const struct counter_timer_config *config)
288 {
289 	NRF_TIMER_Type *reg = get_nrfx_config(dev)->timer;
290 
291 	nrf_timer_bit_width_set(reg, config->bit_width);
292 	nrf_timer_mode_set(reg, config->mode);
293 	nrf_timer_frequency_set(reg, config->freq);
294 
295 	nrf_timer_cc_set(reg, TOP_CH, counter_get_max_top_value(dev));
296 
297 	NRFX_IRQ_ENABLE(NRFX_IRQ_NUMBER_GET(reg));
298 
299 	return 0;
300 }
301 
get_guard_period(const struct device * dev,uint32_t flags)302 static uint32_t get_guard_period(const struct device *dev, uint32_t flags)
303 {
304 	return get_dev_data(dev)->guard_period;
305 }
306 
set_guard_period(const struct device * dev,uint32_t guard,uint32_t flags)307 static int set_guard_period(const struct device *dev, uint32_t guard,
308 			    uint32_t flags)
309 {
310 	__ASSERT_NO_MSG(guard < get_top_value(dev));
311 
312 	get_dev_data(dev)->guard_period = guard;
313 	return 0;
314 }
315 
top_irq_handle(const struct device * dev)316 static void top_irq_handle(const struct device *dev)
317 {
318 	NRF_TIMER_Type *reg = get_nrfx_config(dev)->timer;
319 	counter_top_callback_t cb = get_dev_data(dev)->top_cb;
320 
321 	if (nrf_timer_event_check(reg, COUNTER_TOP_EVT) &&
322 		nrf_timer_int_enable_check(reg, COUNTER_TOP_INT_MASK)) {
323 		nrf_timer_event_clear(reg, COUNTER_TOP_EVT);
324 		__ASSERT(cb != NULL, "top event enabled - expecting callback");
325 		cb(dev, get_dev_data(dev)->top_user_data);
326 	}
327 }
328 
alarm_irq_handle(const struct device * dev,uint32_t id)329 static void alarm_irq_handle(const struct device *dev, uint32_t id)
330 {
331 	uint32_t cc = ID_TO_CC(id);
332 	NRF_TIMER_Type *reg = get_nrfx_config(dev)->timer;
333 	uint32_t int_mask = nrf_timer_compare_int_get(cc);
334 	nrf_timer_event_t evt = nrf_timer_compare_event_get(cc);
335 	bool hw_irq_pending = nrf_timer_event_check(reg, evt) &&
336 			      nrf_timer_int_enable_check(reg, int_mask);
337 	bool sw_irq_pending = get_dev_data(dev)->cc_int_pending & BIT(cc);
338 
339 	if (hw_irq_pending || sw_irq_pending) {
340 		struct counter_nrfx_ch_data *chdata;
341 		counter_alarm_callback_t cb;
342 
343 		nrf_timer_event_clear(reg, evt);
344 		atomic_and(&get_dev_data(dev)->cc_int_pending, ~BIT(cc));
345 		nrf_timer_int_disable(reg, int_mask);
346 
347 		chdata = &get_nrfx_config(dev)->ch_data[id];
348 		cb = chdata->callback;
349 		chdata->callback = NULL;
350 
351 		if (cb) {
352 			uint32_t cc_val = nrf_timer_cc_get(reg, cc);
353 
354 			cb(dev, id, cc_val, chdata->user_data);
355 		}
356 	}
357 }
358 
irq_handler(const struct device * dev)359 static void irq_handler(const struct device *dev)
360 {
361 	top_irq_handle(dev);
362 
363 	for (uint32_t i = 0; i < counter_get_num_of_channels(dev); i++) {
364 		alarm_irq_handle(dev, i);
365 	}
366 }
367 
368 static const struct counter_driver_api counter_nrfx_driver_api = {
369 	.start = start,
370 	.stop = stop,
371 	.get_value = get_value,
372 	.set_alarm = set_alarm,
373 	.cancel_alarm = cancel_alarm,
374 	.set_top_value = set_top_value,
375 	.get_pending_int = get_pending_int,
376 	.get_top_value = get_top_value,
377 	.get_guard_period = get_guard_period,
378 	.set_guard_period = set_guard_period,
379 };
380 
381 /*
382  * Device instantiation is done with node labels due to HAL API
383  * requirements. In particular, TIMERx_MAX_SIZE values from HALs
384  * are indexed by peripheral number, so DT_INST APIs won't work.
385  */
386 
387 #define TIMER(idx)		DT_NODELABEL(timer##idx)
388 #define TIMER_PROP(idx, prop)	DT_PROP(TIMER(idx), prop)
389 
390 #define TIMER_IRQ_CONNECT(idx)						       \
391 	COND_CODE_1(CONFIG_COUNTER_TIMER##idx##_ZLI,			       \
392 		(IRQ_DIRECT_CONNECT(DT_IRQN(TIMER(idx)),		       \
393 				    DT_IRQ(TIMER(idx), priority),	       \
394 				    counter_timer##idx##_isr_wrapper,	       \
395 				    IRQ_ZERO_LATENCY)),			       \
396 		(IRQ_CONNECT(DT_IRQN(TIMER(idx)), DT_IRQ(TIMER(idx), priority),\
397 			    irq_handler, DEVICE_DT_GET(TIMER(idx)), 0))	       \
398 	)
399 
400 #define COUNTER_NRFX_TIMER_DEVICE(idx)					       \
401 	BUILD_ASSERT(TIMER_PROP(idx, prescaler) <=			       \
402 			TIMER_PRESCALER_PRESCALER_Msk,			       \
403 		     "TIMER prescaler out of range");			       \
404 	COND_CODE_1(CONFIG_COUNTER_TIMER##idx##_ZLI, (			       \
405 		ISR_DIRECT_DECLARE(counter_timer##idx##_isr_wrapper)	       \
406 		{							       \
407 			irq_handler(DEVICE_DT_GET(TIMER(idx)));		       \
408 			/* No rescheduling, it shall not access zephyr primitives. */ \
409 			return 0;					       \
410 		}), ())							       \
411 	static int counter_##idx##_init(const struct device *dev)	       \
412 	{								       \
413 		TIMER_IRQ_CONNECT(idx);					       \
414 		static const struct counter_timer_config config = {	       \
415 			.freq = TIMER_PROP(idx, prescaler),		       \
416 			.mode = NRF_TIMER_MODE_TIMER,			       \
417 			.bit_width = (TIMER##idx##_MAX_SIZE == 32) ?	       \
418 					NRF_TIMER_BIT_WIDTH_32 :	       \
419 					NRF_TIMER_BIT_WIDTH_16,		       \
420 		};							       \
421 		return init_timer(dev, &config);			       \
422 	}								       \
423 	static struct counter_nrfx_data counter_##idx##_data;		       \
424 	static struct counter_nrfx_ch_data				       \
425 		counter##idx##_ch_data[CC_TO_ID(TIMER##idx##_CC_NUM)];	       \
426 	LOG_INSTANCE_REGISTER(LOG_MODULE_NAME, idx, CONFIG_COUNTER_LOG_LEVEL); \
427 	static const struct counter_nrfx_config nrfx_counter_##idx##_config = {\
428 		.info = {						       \
429 			.max_top_value = (TIMER##idx##_MAX_SIZE == 32) ?       \
430 					0xffffffff : 0x0000ffff,	       \
431 			.freq = TIMER_CLOCK /				       \
432 					(1 << TIMER_PROP(idx, prescaler)),     \
433 			.flags = COUNTER_CONFIG_INFO_COUNT_UP,		       \
434 			.channels = CC_TO_ID(TIMER##idx##_CC_NUM),	       \
435 		},							       \
436 		.ch_data = counter##idx##_ch_data,			       \
437 		.timer = (NRF_TIMER_Type *)DT_REG_ADDR(TIMER(idx)),	       \
438 		LOG_INSTANCE_PTR_INIT(log, LOG_MODULE_NAME, idx)	       \
439 	};								       \
440 	DEVICE_DT_DEFINE(TIMER(idx),					       \
441 			    counter_##idx##_init,			       \
442 			    NULL,					       \
443 			    &counter_##idx##_data,			       \
444 			    &nrfx_counter_##idx##_config.info,		       \
445 			    PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,  \
446 			    &counter_nrfx_driver_api)
447 
448 #ifdef CONFIG_COUNTER_TIMER0
449 COUNTER_NRFX_TIMER_DEVICE(0);
450 #endif
451 
452 #ifdef CONFIG_COUNTER_TIMER1
453 COUNTER_NRFX_TIMER_DEVICE(1);
454 #endif
455 
456 #ifdef CONFIG_COUNTER_TIMER2
457 COUNTER_NRFX_TIMER_DEVICE(2);
458 #endif
459 
460 #ifdef CONFIG_COUNTER_TIMER3
461 COUNTER_NRFX_TIMER_DEVICE(3);
462 #endif
463 
464 #ifdef CONFIG_COUNTER_TIMER4
465 COUNTER_NRFX_TIMER_DEVICE(4);
466 #endif
467