1/*
2 * Copyright (c) 2017, Erwin Rol <erwin@erwinrol.com>
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7/dts-v1/;
8#include <st/f4/stm32f407Xg.dtsi>
9#include <st/f4/stm32f407z(e-g)tx-pinctrl.dtsi>
10
11/ {
12	model = "Olimex STM32-E407 board";
13	compatible = "olimex,stm32-e407";
14
15	chosen {
16		zephyr,console = &usart1;
17		zephyr,shell-uart = &usart1;
18		zephyr,sram = &sram0;
19		zephyr,flash = &flash0;
20		zephyr,ccm = &ccm0;
21	};
22
23	leds {
24		compatible = "gpio-leds";
25		green_led_1: led_1 {
26			gpios = <&gpioc 13 GPIO_ACTIVE_HIGH>;
27			label = "LED1";
28		};
29	};
30
31	gpio_keys {
32		compatible = "gpio-keys";
33		user_button: button {
34			label = "Key";
35			gpios = <&gpioa 0 GPIO_ACTIVE_LOW>;
36		};
37	};
38
39	aliases {
40		led0 = &green_led_1;
41		sw0 = &user_button;
42	};
43};
44
45&clk_hse {
46	clock-frequency = <DT_FREQ_M(12)>;
47	status = "okay";
48};
49
50&pll {
51	div-m = <6>;
52	mul-n = <168>;
53	div-p = <2>;
54	div-q = <7>;
55	clocks = <&clk_hse>;
56	status = "okay";
57};
58
59&rcc {
60	clocks = <&pll>;
61	clock-frequency = <DT_FREQ_M(168)>;
62	ahb-prescaler = <1>;
63	apb1-prescaler = <4>;
64	apb2-prescaler = <2>;
65};
66
67&usart1 {
68	pinctrl-0 = <&usart1_tx_pb6 &usart1_rx_pb7>;
69	current-speed = <115200>;
70	status = "okay";
71};
72
73&usart3 {
74	pinctrl-0 = <&usart3_tx_pb10 &usart3_rx_pb11>;
75	current-speed = <115200>;
76	status = "okay";
77};
78
79&usart6 {
80	pinctrl-0 = <&usart6_tx_pc6 &usart6_rx_pc7>;
81	current-speed = <115200>;
82	status = "okay";
83};
84
85&rtc {
86	status = "okay";
87};
88
89&rng {
90	status = "okay";
91};
92
93/* Only one interface should be enabled at a time: usbotg_fs or usbotg_hs */
94usb_otg1: &usbotg_fs {
95	pinctrl-0 = <&usb_otg_fs_dm_pa11 &usb_otg_fs_dp_pa12>;
96	status = "disabled";
97};
98
99zephyr_udc0: &usbotg_hs {
100	pinctrl-0 = <&usb_otg_hs_dm_pb14 &usb_otg_hs_dp_pb15>;
101	status = "okay";
102};
103
104&mac {
105	status = "okay";
106	pinctrl-0 = <&eth_mdc_pc1
107		     &eth_rxd0_pc4
108		     &eth_rxd1_pc5
109		     &eth_ref_clk_pa1
110		     &eth_mdio_pa2
111		     &eth_col_pa3
112		     &eth_crs_dv_pa7
113		     &eth_tx_en_pg11
114		     &eth_txd0_pg13
115		     &eth_txd1_pg14>;
116};
117