1.. _mec17sxevb_assy6906: 2 3MEC172xEVB ASSY6906 4################### 5 6Overview 7******** 8 9The MEC172xEVB_ASSY6906 kit is a future development platform to evaluate the 10Microchip MEC172X series microcontrollers. This board needs to be mated with 11part number MEC1723 176WFBA SOLDER DC ASSY 6915(cpu board) in order to operate. 12MEC172x and MEC152x SPI image formats are not compatible with each other. 13 14Hardware 15******** 16 17- MEC1723NB0SZ ARM Cortex-M4 Processor 18- 416 KB RAM and 128 KB boot ROM 19- Keyboard interface 20- ADC & GPIO headers 21- UART0 and UART1 22- FAN0, FAN1, FAN2 headers 23- FAN PWM interface 24- JTAG/SWD, ETM and MCHP Trace ports 25- PECI interface 3.0 26- I2C voltage translator 27- 10 SMBUS headers 28- 4 SGPIO headers 29- VCI interface 30- 2 independent Hardware Driven PS/2 Ports 31- eSPI header 32- 3 Breathing/Blinking LEDs 33- 2 Sockets for SPI NOR chips 34- One reset and VCC_PWRDGD pushbuttons 35- One external PCA9555 I/O port with jumper selectable I2C address. 36- One external LTC2489 delta-sigma ADC with jumper selectable I2C address. 37- Board power jumper selectable from +5V 2.1mm/5.5mm barrel connector or USB Micro A connector. 38 39For more information about the SOC's please see `MEC172x Reference Manual`_ 40 41Supported Features 42================== 43 44The mec172xevb_assy6906 board configuration supports the following hardware 45features: 46 47+-----------+------------+-------------------------------------+ 48| Interface | Controller | Driver/Component | 49+===========+============+=====================================+ 50| NVIC | on-chip | nested vector interrupt controller | 51+-----------+------------+-------------------------------------+ 52| SYSTICK | on-chip | systick | 53+-----------+------------+-------------------------------------+ 54| UART | on-chip | serial port | 55+-----------+------------+-------------------------------------+ 56| GPIO | on-chip | gpio | 57+-----------+------------+-------------------------------------+ 58| I2C | on-chip | i2c | 59+-----------+------------+-------------------------------------+ 60| PINMUX | on-chip | pinmux | 61+-----------+------------+-------------------------------------+ 62| PS/2 | on-chip | ps2 | 63+-----------+------------+-------------------------------------+ 64| KSCAN | on-chip | kscan | 65+-----------+------------+-------------------------------------+ 66| TACH | on-chip | tachometer | 67+-----------+------------+-------------------------------------+ 68| RPMFAN | on-chip | Fan speed controller | 69+-----------+------------+-------------------------------------+ 70 71 72 73 74Other hardware features are not currently supported by Zephyr (at the moment) 75 76The default configuration can be found in the 77:zephyr_file:`boards/arm/mec172xevb_assy6906/mec172xevb_assy6906_defconfig` Kconfig file. 78 79Connections and IOs 80=================== 81 82This evaluation board kit is comprised of the following HW blocks: 83 84- MEC172x EVB ASSY 6906 Rev A `MEC172x EVB Schematic`_ 85- MEC1723 176WFBA SOLDER DC ASSY 6915 with MEC172x silicon `MEC172x Daughter Card Schematic`_ 86- SPI DONGLE ASSY 6791 `SPI Dongle Schematic`_ 87 88System Clock 89============ 90 91The MEC1723 MCU is configured to use the 96Mhz internal oscillator with the 92on-chip PLL to generate a resulting EC clock rate of 12 MHz. See Processor clock 93control register in chapter 4 "4.0 POWER, CLOCKS, and RESETS" of the data sheet in 94the references at the end of this document. 95 96Serial Port 97=========== 98 99UART1 is configured for serial logs. 100 101Jumper settings 102*************** 103 104Please follow the jumper settings below to properly demo this 105board. Advanced users may deviate from this recommendation. 106 107Jumper setting for MEC172x EVB Assy 6906 Rev A1p0 108================================================= 109 110Power-related jumpers 111--------------------- 112 113If you wish to power from +5V power brick, then connect to barrel connector ``P11`` 114(5.5mm OD, 2.1mm ID) and move the jumper to ``JP88 5-6``. 115 116If you wish to power from micro-USB type A/B connector ``P12``, move the 117jumper to ``JP88 7-8``. 118 119 120.. note:: A single jumper is required in JP88. 121 122+-------+------+------+------+------+------+------+------+------+------+------+ 123| JP22 | JP32 | JP33 | JP37 | JP43 | JP47 | JP54 | JP56 | JP58 | JP64 | JP65 | 124+=======+======+======+======+======+======+======+======+======+======+======+ 125| 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 126+-------+------+------+------+------+------+------+------+------+------+------+ 127 128+------+------+------+------+------+------+------+------+------+------+ 129| JP72 | JP73 | JP76 | JP79 | JP80 | JP81 | JP82 | JP84 | JP87 | JP89 | 130+======+======+======+======+======+======+======+======+======+======+ 131| 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 132+------+------+------+------+------+------+------+------+------+------+ 133 134+------+------+-------+-------+-------+ 135| JP90 | JP91 | JP100 | JP101 | JP118 | 136+======+======+=======+=======+=======+ 137| 1-2 | 1-2 | 1-2 | 1-2 | 2-3 | 138+------+------+-------+-------+-------+ 139 140These jumpers configure VCC Power good, nRESETI and JTAG_STRAP respectively. 141 142+------------------+-----------+--------------+ 143| JP5 | JP4 | JP45 | 144| (VCC Power good) | (nRESETI) | (JTAG_STRAP) | 145+==================+===========+==============+ 146| 1-2 | 1-2 | 2-3 | 147+------------------+-----------+--------------+ 148 149Boot-ROM Straps. 150---------------- 151 152These jumpers configure MEC1501 Boot-ROM straps. 153 154+-------------+------------+--------------+-------------+ 155| JP93 | JP11 | JP46 | JP96 | 156| (CMP_STRAP) | (CR_STRAP) | (VTR2_STRAP) | (BSS_STRAP) | 157+=============+============+==============+=============+ 158| 2-3 | 1-2 | 2-3 | 1-2 | 159+-------------+------------+--------------+-------------+ 160 161``JP96 1-2`` pulls SHD SPI CS0# up to VTR2. MEC172x Boot-ROM samples 162SHD SPI CS0# and if high, it loads code from SHD SPI. 163 164Peripheral Routing Jumpers 165-------------------------- 166 167Each column of the following table illustrates how to enable UART1, SWD, 168PVT SPI, SHD SPI and LED0-2 respectively. 169 170+----------+----------+--------+-----------+----------+---------+ 171| JP48 | JP9 | JP9 | JP38 | JP98 | JP41 | 172| (UART1) | (UART1) | (SWD) | (PVT SPI) | (SHD SPI)| (LED0-2)| 173+==========+==========+========+===========+==========+=========+ 174| 1-2 | | 2-3 | 2-3 | 2-3 | 1-2 | 175+----------+----------+--------+-----------+----------+---------+ 176| 4-5 | 4-5 | | 5-6 | 5-6 | 3-4 | 177+----------+----------+--------+-----------+----------+---------+ 178| 7-8 | | 8-9 | 8-9 | 8-9 | 5-6 | 179+----------+----------+--------+-----------+----------+---------+ 180| 10-11 | 10-11 | | 11-12 | 11-12 | | 181+----------+----------+--------+-----------+----------+---------+ 182| | | | 14-15 | 14-15 | | 183+----------+----------+--------+-----------+----------+---------+ 184| | | | 17-18 | 20-21 | | 185+----------+----------+--------+-----------+----------+---------+ 186 187.. note:: For UART1 make sure JP39 have jumpers connected 1-2, 3-4. 188 189To receive UART1 serial output, please refer to the picture below 190to make sure that JP9 configured for UART1 output. 191 192Jumper settings for MEC172x 176WFBGA Socket DC Assy 6915 Rev B1p0 193================================================================= 194 195The jumper configuration explained above covers the base board. The ASSY 1966915 MEC1723 CPU board provides capability for an optional, external 32KHz 197clock source. The card includes a 32KHz crystal oscillator. The card can 198also be configured to use an external 50% duty cycle 32KHz source on the 199XTAL2/32KHZ_IN pin. Note, firmware must set the MEC172x clock enable 200register to select the external source matching the jumper settings. If 201using the MEC15xx internal silicon oscillator then the 32K jumper settings 202are don't cares. ``JP1`` is for scoping test clock outputs. Please refer to 203the schematic in reference section below. 204 205Parallel 32KHz crystal configuration 206------------------------------------ 207+-------+-------+ 208| JP2 | JP3 | 209+=======+=======+ 210| 1-2 | 2-3 | 211+-------+-------+ 212 213External 32KHz 50% duty cycle configuration 214------------------------------------------- 215+-------+-------+ 216| JP2 | JP3 | 217+=======+=======+ 218| NC | 1-2 | 219+-------+-------+ 220 221 222Jumper settings for MEC1723 176WFBGA Socket DC Assy 6915 Rev B1p0 223================================================================= 224 225The MEC1723 ASSY 6915 CPU card does not include an onboard external 22632K crystal or oscillator. The one jumper block ``JP1`` is for scoping 227test clock outputs not for configuration. Please refer to schematic 228in reference section below. 229 230Programming and Debugging 231************************* 232 233Setup 234===== 235#. If you use Dediprog SF100 programmer, then setup it. 236 237 Windows version can be found at the `SF100 Product page`_. 238 239 Linux version source code can be found at `SF100 Linux GitHub`_. 240 Follow the `SF100 Linux manual`_ to complete setup of the SF100 programmer. 241 For Linux please make sure that you copied ``60-dediprog.rules`` 242 from the ``SF100Linux`` folder to the :code:`/etc/udev/rules.s` (or rules.d) 243 then restart service using: 244 245 .. code-block:: console 246 247 $ udevadm control --reload 248 249 Add directory with program ``dpcmd`` (on Linux) 250 or ``dpcmd.exe`` (on Windows) to your ``PATH``. 251 252#. Clone the `MEC172x SPI Image Gen`_ repository or download the files within 253 that directory. 254 255#. Make the image generation available for Zephyr, by making the tool 256 searchable by path, or by setting an environment variable 257 ``MEC172X_SPI_GEN``, for example: 258 259 .. code-block:: console 260 261 export MEC172X_SPI_GEN=<path to tool>/mec172x_spi_gen_lin_x86_64 262 263 Note that the tools for Linux and Windows have different file names. 264 265#. If needed, a custom SPI image configuration file can be specified 266 to override the default one. 267 268 .. code-block:: console 269 270 export MEC172X_SPI_CFG=custom_spi_cfg.txt 271 272Wiring 273======== 274#. Connect the SPI Dongle ASSY 6791 to ``J34`` in the EVB. 275 276#. Connect programmer to the header J6 on the Assy6791 board, it will flash the SPI NOR chip ``U3`` 277 Make sure that your programmer's offset is 0x0. 278 For programming you can use Dediprog SF100 or a similar tool for flashing SPI chips. 279 280 281 .. note:: Remember that SPI MISO/MOSI are swapped on Dediprog headers! 282 Use separate wires to connect Dediprog pins with pins on the Assy6791 SPI board. 283 Wiring connection is described in the table below. 284 285 +------------+---------------+ 286 | Dediprog | Assy6791 | 287 | Connector | J6 Connector | 288 +============+===============+ 289 | VCC | 1 | 290 +------------+---------------+ 291 | GND | 2 | 292 +------------+---------------+ 293 | CS | 3 | 294 +------------+---------------+ 295 | CLK | 4 | 296 +------------+---------------+ 297 | MISO | 6 | 298 +------------+---------------+ 299 | MOSI | 5 | 300 +------------+---------------+ 301 302#. Connect UART1 port of the MEC17xxEVB_ASSY_6906 board 303 to your host computer using the RS232 cable. 304 305#. Apply power to the board via a micro-USB cable. 306 Configure this option by using a jumper between ``JP88 7-8``. 307 308#. Final wiring for the board should look like this: 309 310Building 311======== 312#. Build :ref:`hello_world` application as you would normally do. 313 314#. The file :file:`spi_image.bin` will be created if the build system 315 can find the image generation tool. This binary image can be used 316 to flash the SPI chip. 317 318Flashing 319======== 320#. Run your favorite terminal program to listen for output. 321 Under Linux the terminal should be :code:`/dev/ttyUSB0`. Do not close it. 322 323 For example: 324 325 .. code-block:: console 326 327 $ minicom -D /dev/ttyUSB0 -o 328 329 The -o option tells minicom not to send the modem initialization 330 string. Connection should be configured as follows: 331 332 - Speed: 115200 333 - Data: 8 bits 334 - Parity: None 335 - Stop bits: 1 336 337#. Flash your board using ``west`` from the second terminal window. 338 Split first and second terminal windows to view both of them. 339 340 .. code-block:: console 341 342 $ west flash 343 344 .. note:: When west process started press Reset button and do not release it 345 till the whole west process will not be finished successfully. 346 347 348 .. note:: If you dont't want to press Reset button every time, you can disconnect 349 SPI Dongle ASSY 6791 from the EVB during the west flash programming. 350 Then connect it back to the ``J34`` header and apply power to the EVB. 351 Result will be the same. 352 353 354#. You should see ``"Hello World! mec172xevb_assy6906"`` in the first terminal window. 355 If you don't see this message, press the Reset button and the message should appear. 356 357Debugging 358========= 359This board comes with a Cortex ETM port which facilitates tracing and debugging 360using a single physical connection. In addition, it comes with sockets for 361JTAG only sessions. 362 363Troubleshooting 364=============== 365#. In case you don't see your application running, please make sure ``LED7``, ``LED8``, and ``LED1`` 366 are lit. If one of these is off, then check the power-related jumpers again. 367 368#. If you can't program the board using Dediprog, disconnect the Assy6791 369 from the main board Assy6853 and try again. 370 371#. If Dediprog can't detect the onboard flash, press the board's Reset button and try again. 372 373References 374********** 375.. target-notes:: 376 377.. _MEC172x Reference Manual: 378 https://github.com/MicrochipTech/CPGZephyrDocs/blob/master/MEC172x/MEC172x-Data-Sheet.pdf 379.. _MEC172x EVB Schematic: 380 https://github.com/MicrochipTech/CPGZephyrDocs/blob/master/MEC172x/MEC172X-EVB-Assy_6906-A1p0-SCH.pdf 381.. _MEC172x Daughter Card Schematic: 382 https://github.com/MicrochipTech/CPGZephyrDocs/blob/master/MEC172x/MEC172X-176WFBGA-Socket-DC-Assy6915-Rev-B-SCH.pdf 383.. _SPI Dongle Schematic: 384 https://github.com/MicrochipTech/CPGZephyrDocs/blob/master/MEC1501/SPI%20Dongles%20and%20Aardvark%20Interposer%20Assy%206791%20Rev%20A1p1%20-%20SCH.pdf 385.. _MEC172x SPI Image Gen: 386 https://github.com/MicrochipTech/CPGZephyrDocs/tree/master/MEC172x/SPI_image_gen 387.. _SF100 Linux GitHub: 388 https://github.com/DediProgSW/SF100Linux 389.. _SF100 Product page: 390 https://www.dediprog.com/product/SF100 391.. _SF100 Linux manual: 392 https://www.dediprog.com/download/save/727.pdf 393
