1 /* 2 * Copyright (c) 2019 Intel Corporation 3 * SPDX-License-Identifier: Apache-2.0 4 */ 5 6 #ifndef ZEPHYR_ARCH_X86_INCLUDE_KERNEL_ARCH_DATA_H_ 7 #define ZEPHYR_ARCH_X86_INCLUDE_KERNEL_ARCH_DATA_H_ 8 9 /* 10 * Exception/interrupt vector definitions: vectors 20 to 31 are reserved 11 * for Intel; vectors 32 to 255 are user defined interrupt vectors. 12 */ 13 14 #define IV_DIVIDE_ERROR 0 15 #define IV_DEBUG 1 16 #define IV_NON_MASKABLE_INTERRUPT 2 17 #define IV_BREAKPOINT 3 18 #define IV_OVERFLOW 4 19 #define IV_BOUND_RANGE 5 20 #define IV_INVALID_OPCODE 6 21 #define IV_DEVICE_NOT_AVAILABLE 7 22 #define IV_DOUBLE_FAULT 8 23 #define IV_COPROC_SEGMENT_OVERRUN 9 24 #define IV_INVALID_TSS 10 25 #define IV_SEGMENT_NOT_PRESENT 11 26 #define IV_STACK_FAULT 12 27 #define IV_GENERAL_PROTECTION 13 28 #define IV_PAGE_FAULT 14 29 #define IV_RESERVED 15 30 #define IV_X87_FPU_FP_ERROR 16 31 #define IV_ALIGNMENT_CHECK 17 32 #define IV_MACHINE_CHECK 18 33 #define IV_SIMD_FP 19 34 #define IV_VIRT_EXCEPTION 20 35 #define IV_SECURITY_EXCEPTION 30 36 37 #define IV_IRQS 32 /* start of vectors available for IRQs */ 38 #define IV_NR_VECTORS 256 /* total number of vectors */ 39 40 /* 41 * EFLAGS/RFLAGS definitions. (RFLAGS is just zero-extended EFLAGS.) 42 */ 43 44 #define EFLAGS_IF BIT(9) /* interrupts enabled */ 45 #define EFLAGS_DF BIT(10) /* Direction flag */ 46 47 #define EFLAGS_INITIAL (EFLAGS_IF) 48 #define EFLAGS_SYSCALL (EFLAGS_IF | EFLAGS_DF) 49 /* 50 * Control register definitions. 51 */ 52 53 #define CR0_PG BIT(31) /* enable paging */ 54 #define CR0_WP BIT(16) /* honor W bit even when supervisor */ 55 56 #define CR4_PSE BIT(4) /* Page size extension (4MB pages) */ 57 #define CR4_PAE BIT(5) /* enable PAE */ 58 #define CR4_OSFXSR BIT(9) /* enable SSE (OS FXSAVE/RSTOR) */ 59 60 #ifdef CONFIG_X86_64 61 #include <intel64/kernel_arch_data.h> 62 #else 63 #include <ia32/kernel_arch_data.h> 64 #endif 65 66 #endif /* ZEPHYR_ARCH_X86_INCLUDE_KERNEL_ARCH_DATA_H_ */ 67
