1 /*
2 * Copyright (c) 2020 Intel Corporation
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include <kernel.h>
8 #include <sys/device_mmio.h>
9 #include <sys/util.h>
10 #include <drivers/pcie/pcie.h>
11 #include <soc.h>
12
13
14 #ifdef UART_NS16550_ACCESS_IOPORT
15 /* Legacy I/O Port Access to a NS16550 UART */
16 #define IN(reg) sys_in8(reg + UART_NS16550_ACCESS_IOPORT)
17 #define OUT(reg, val) sys_out8(val, reg + UART_NS16550_ACCESS_IOPORT)
18 #elif defined(X86_SOC_EARLY_SERIAL_PCIDEV)
19 /* "Modern" mapping of a UART into a PCI MMIO device. The registers
20 * are still bytes, but spaced at a 32 bit stride instead of packed
21 * together.
22 */
23 static mm_reg_t mmio;
24 #define IN(reg) (sys_read32(mmio + reg * 4) & 0xff)
25 #define OUT(reg, val) sys_write32((val) & 0xff, mmio + reg * 4)
26 #elif defined(X86_SOC_EARLY_SERIAL_MMIO8_ADDR)
27 /* Still other devices use a MMIO region containing packed byte
28 * registers
29 */
30 #ifdef DEVICE_MMIO_IS_IN_RAM
31 static mm_reg_t mmio;
32 #define BASE mmio
33 #else
34 #define BASE X86_SOC_EARLY_SERIAL_MMIO8_ADDR
35 #endif /* DEVICE_MMIO_IS_IN_RAM */
36 #define IN(reg) sys_read8(BASE + reg)
37 #define OUT(reg, val) sys_write8(val, BASE + reg)
38 #else
39 #error "Unsupported configuration"
40 #endif
41
42 #define REG_THR 0x00 /* Transmitter holding reg. */
43 #define REG_IER 0x01 /* Interrupt enable reg. */
44 #define REG_FCR 0x02 /* FIFO control reg. */
45 #define REG_LCR 0x03 /* Line control reg. */
46 #define REG_MCR 0x04 /* Modem control reg. */
47 #define REG_LSR 0x05 /* Line status reg. */
48 #define REG_BRDL 0x00 /* Baud rate divisor (LSB) */
49 #define REG_BRDH 0x01 /* Baud rate divisor (MSB) */
50
51 #define IER_DISABLE 0x00
52 #define LCR_8N1 (BIT(0) | BIT(1))
53 #define LCR_DLAB_SELECT BIT(7)
54 #define MCR_DTR BIT(0)
55 #define MCR_RTS BIT(1)
56 #define LSR_THRE BIT(5)
57
58 #define FCR_FIFO BIT(0) /* enable XMIT and RCVR FIFO */
59 #define FCR_RCVRCLR BIT(1) /* clear RCVR FIFO */
60 #define FCR_XMITCLR BIT(2) /* clear XMIT FIFO */
61 #define FCR_FIFO_1 0 /* 1 byte in RCVR FIFO */
62
63 static bool early_serial_init_done;
64 static uint32_t suppressed_chars;
65
serout(int c)66 static void serout(int c)
67 {
68 while ((IN(REG_LSR) & LSR_THRE) == 0) {
69 }
70 OUT(REG_THR, c);
71 }
72
arch_printk_char_out(int c)73 int arch_printk_char_out(int c)
74 {
75 if (!early_serial_init_done) {
76 suppressed_chars++;
77 return c;
78 }
79
80 if (c == '\n') {
81 serout('\r');
82 }
83 serout(c);
84 return c;
85 }
86
z_x86_early_serial_init(void)87 void z_x86_early_serial_init(void)
88 {
89 #if defined(DEVICE_MMIO_IS_IN_RAM) && !defined(UART_NS16550_ACCESS_IOPORT)
90 #ifdef X86_SOC_EARLY_SERIAL_PCIDEV
91 struct pcie_mbar mbar;
92 pcie_get_mbar(X86_SOC_EARLY_SERIAL_PCIDEV, 0, &mbar);
93 pcie_set_cmd(X86_SOC_EARLY_SERIAL_PCIDEV, PCIE_CONF_CMDSTAT_MEM, true);
94 device_map(&mmio, mbar.phys_addr, mbar.size, K_MEM_CACHE_NONE);
95 #else
96 device_map(&mmio, X86_SOC_EARLY_SERIAL_MMIO8_ADDR, 0x1000, K_MEM_CACHE_NONE);
97 #endif
98
99 #endif /* DEVICE_MMIO_IS_IN_RAM */
100
101 OUT(REG_IER, IER_DISABLE); /* Disable interrupts */
102 OUT(REG_LCR, LCR_DLAB_SELECT); /* DLAB select */
103 OUT(REG_BRDL, 1); /* Baud divisor = 1 */
104 OUT(REG_BRDH, 0);
105 OUT(REG_LCR, LCR_8N1); /* LCR = 8n1 + DLAB off */
106 OUT(REG_MCR, MCR_DTR | MCR_RTS);
107
108 /* Turn on FIFO. Some hardware needs this before transmitting */
109 OUT(REG_FCR, FCR_FIFO | FCR_FIFO_1 | FCR_RCVRCLR | FCR_XMITCLR);
110
111 early_serial_init_done = true;
112
113 if (suppressed_chars != 0U) {
114 printk("WARNING: %u chars lost before early serial init\n",
115 suppressed_chars);
116 }
117 }
118
