1 /*
2  * Copyright (c) 2019 Carlo Caione <ccaione@baylibre.com>
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 /**
8  * @file
9  * @brief Exception/interrupt context helpers for Cortex-A CPUs
10  *
11  * Exception/interrupt context helpers.
12  */
13 
14 #ifndef ZEPHYR_ARCH_ARM64_INCLUDE_EXC_H_
15 #define ZEPHYR_ARCH_ARM64_INCLUDE_EXC_H_
16 
17 #include <arch/cpu.h>
18 
19 #ifdef _ASMLANGUAGE
20 
21 /* nothing */
22 
23 #else
24 
25 #include <irq_offload.h>
26 
27 #ifdef __cplusplus
28 extern "C" {
29 #endif
30 
31 #if defined(CONFIG_IRQ_OFFLOAD)
32 extern void z_arm64_offload(void);
33 #endif
34 
arch_is_in_isr(void)35 static ALWAYS_INLINE bool arch_is_in_isr(void)
36 {
37 	return arch_curr_cpu()->nested != 0U;
38 }
39 
40 
41 extern void z_arm64_call_svc(void *switch_to, void **switched_from);
42 
43 #ifdef __cplusplus
44 }
45 #endif
46 
47 #endif /* _ASMLANGUAGE */
48 
49 #endif /* ZEPHYR_ARCH_ARM64_INCLUDE_EXC_H_ */
50