1# Copyright (c) 2024 Intel Corp.
2# SPDX-License-Identifier: Apache-2.0
3#
4menu "SMP Options"
5
6config SMP
7	bool "Symmetric multiprocessing support"
8	depends on USE_SWITCH
9	depends on !ATOMIC_OPERATIONS_C
10	help
11	  When true, kernel will be built with SMP support, allowing
12	  more than one CPU to schedule Zephyr tasks at a time.
13
14config USE_SWITCH
15	bool "Use new-style _arch_switch instead of arch_swap"
16	depends on USE_SWITCH_SUPPORTED
17	help
18	  The _arch_switch() API is a lower level context switching
19	  primitive than the original arch_swap mechanism.  It is required
20	  for an SMP-aware scheduler, or if the architecture does not
21	  provide arch_swap.  In uniprocess situations where the
22	  architecture provides both, _arch_switch incurs more somewhat
23	  overhead and may be slower.
24
25config USE_SWITCH_SUPPORTED
26	bool
27	help
28	  Indicates whether _arch_switch() API is supported by the
29	  currently enabled platform. This option should be selected by
30	  platforms that implement it.
31
32config SMP_BOOT_DELAY
33	bool "Delay booting secondary cores"
34	depends on SMP
35	help
36	  By default Zephyr will boot all available CPUs during start up.
37	  Select this option to skip this and allow custom code
38	  (architecture/SoC/board/application) to boot secondary CPUs at
39	  a later time.
40
41config MP_MAX_NUM_CPUS
42	int "Maximum number of CPUs/cores"
43	default 1
44	range 1 12
45	help
46	  Maximum number of multiprocessing-capable cores available to the
47	  multicpu API and SMP features.
48
49config SCHED_IPI_SUPPORTED
50	bool
51	select EVENTS
52	help
53	  True if the architecture supports a call to arch_sched_broadcast_ipi()
54	  to broadcast an interrupt that will call z_sched_ipi() on other CPUs
55	  in the system.  Required for k_thread_abort() to operate with
56	  reasonable latency (otherwise we might have to wait for the other
57	  thread to take an interrupt, which can be arbitrarily far in the
58	  future).
59
60config SCHED_IPI_CASCADE
61	bool "Use cascading IPIs to correct localized scheduling"
62	depends on SCHED_CPU_MASK && !SCHED_CPU_MASK_PIN_ONLY
63	default n
64	help
65	  Threads that are preempted by a local thread (a thread that is
66	  restricted by its CPU mask to execute on a subset of all CPUs) may
67	  trigger additional IPIs when the preempted thread is of higher
68	  priority than a currently executing thread on another CPU. Although
69	  these cascading IPIs will ensure that the system will settle upon a
70	  valid set of high priority threads, it comes at a performance cost.
71
72config TRACE_SCHED_IPI
73	bool "Test IPI"
74	help
75	  When true, it will add a hook into z_sched_ipi(), in order
76	  to check if schedule IPI has called or not, for testing
77	  purpose.
78	depends on SCHED_IPI_SUPPORTED
79	depends on MP_MAX_NUM_CPUS>1
80
81config IPI_OPTIMIZE
82	bool "Optimize IPI delivery"
83	default n
84	depends on SCHED_IPI_SUPPORTED && MP_MAX_NUM_CPUS>1
85	help
86	  When selected, the kernel will attempt to determine the minimum
87	  set of CPUs that need an IPI to trigger a reschedule in response to
88	  a thread newly made ready for execution. This increases the
89	  computation required at every scheduler operation by a value that is
90	  O(N) in the number of CPUs, and in exchange reduces the number of
91	  interrupts delivered. Which to choose is going to depend on
92	  application behavior. If the architecture also supports directing
93	  IPIs to specific CPUs then this has the potential to significantly
94	  reduce the number of IPIs (and consequently ISRs) processed by the
95	  system as the number of CPUs increases. If not, the only benefit
96	  would be to not issue any IPIs if the newly readied thread is of
97	  lower priority than all the threads currently executing on other CPUs.
98
99config KERNEL_COHERENCE
100	bool "Place all shared data into coherent memory"
101	depends on CACHE_CAN_SAY_MEM_COHERENCE
102	default y if SMP && MP_MAX_NUM_CPUS > 1
103	select THREAD_STACK_INFO
104	help
105	  When available and selected, the kernel will build in a mode
106	  where all shared data is placed in multiprocessor-coherent
107	  (generally "uncached") memory.  Thread stacks will remain
108	  cached, as will application memory declared with
109	  __incoherent.  This is intended for Zephyr SMP kernels
110	  running on cache-incoherent architectures only.  Note that
111	  when this is selected, there is an implicit API change that
112	  assumes cache coherence to any memory passed to the kernel.
113	  Code that creates kernel data structures in uncached regions
114	  may fail strangely.  Some assertions exist to catch these
115	  mistakes, but not all circumstances can be tested.
116
117config TICKET_SPINLOCKS
118	bool "Ticket spinlocks for lock acquisition fairness [EXPERIMENTAL]"
119	select EXPERIMENTAL
120	help
121	  Basic spinlock implementation is based on single
122	  atomic variable and doesn't guarantee locking fairness
123	  across multiple CPUs. It's even possible that single CPU
124	  will win the contention every time which will result
125	  in a live-lock.
126	  Ticket spinlocks provide a FIFO order of lock acquisition
127	  which resolves such unfairness issue at the cost of slightly
128	  increased memory footprint.
129
130endmenu
131