1 /*
2 * Copyright (c) 2019 Intel Corporation
3 * Copyright (c) 2019 Microchip Technology Incorporated
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT microchip_xec_rtos_timer
8
9 #include <zephyr/init.h>
10 #include <zephyr/devicetree.h>
11 #include <soc.h>
12 #include <zephyr/arch/common/sys_io.h>
13 #include <zephyr/drivers/timer/system_timer.h>
14 #include <zephyr/sys_clock.h>
15 #include <zephyr/spinlock.h>
16 #include <cmsis_core.h>
17 #include <zephyr/irq.h>
18
19 BUILD_ASSERT(!IS_ENABLED(CONFIG_SMP), "XEC RTOS timer doesn't support SMP");
20 BUILD_ASSERT(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC == 32768,
21 "XEC RTOS timer HW frequency is fixed at 32768");
22
23 /* Microchip MEC 32-bit RTOS timer runs on the 32 KHz always on clock.
24 * It is a downcounter with auto-reload capability.
25 */
26 #define TIMER_CNT_OFS 0 /* R/W counter */
27 #define TIMER_PRLD_OFS 4u /* R/W preload value */
28 #define TIMER_CR_OFS 8u /* R/W control */
29 #define TIMER_CR_ACTV_POS 0 /* activate block */
30 #define TIMER_CR_ARL_EN_POS 1 /* auto-reload enable */
31 #define TIMER_CR_START_POS 2 /* start timer counting */
32 #define TIMER_CR_HDBA_POS 3 /* Halt counting if debugger not in reset */
33 #define TIMER_CR_HALT_POS 4 /* Halt if written to 1, unhalt by clearing */
34
35 /* MEC GIRQ */
36 #define GIRQ_SIZE 20u /* Each GIRQx is 5 32-bit registers */
37 #define GIRQ_SRC_OFS 0 /* R/W1C latched status bits */
38 #define GIRQ_ENSET_OFS 4u /* read, write 1 to set enable bit(s) */
39 #define GIRQ_RESULT_OFS 8u /* R/O bitwise AND of SRC and ENSET */
40 #define GIRQ_ENCLR_OFS 12u /* read, write 1 to clear enable bit(s) */
41
42 #define DEBUG_RTOS_TIMER 0
43
44 #if DEBUG_RTOS_TIMER != 0
45 /* Enable feature to halt timer on JTAG/SWD CPU halt */
46 #define TIMER_START_VAL (BIT(TIMER_CR_ACTV_POS) | BIT(TIMER_CR_START_POS) | BIT(TIMER_CR_HALT_POS))
47 #else
48 #define TIMER_START_VAL (BIT(TIMER_CR_ACTV_POS) | BIT(TIMER_CR_START_POS))
49 #endif
50
51 /*
52 * Overview:
53 *
54 * This driver enables the Microchip XEC 32KHz based RTOS timer as the Zephyr
55 * system timer. It supports both legacy ("tickful") mode as well as
56 * TICKLESS_KERNEL. The XEC RTOS timer is a down counter with a fixed
57 * frequency of 32768 Hz. The driver is based upon the Intel local APIC
58 * timer driver.
59 * Configuration:
60 *
61 * CONFIG_MCHP_XEC_RTOS_TIMER=y
62 *
63 * CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=<hz> must be set to 32768.
64 *
65 * To reduce truncation errors from accumulating due to conversion
66 * to/from time, ticks, and HW cycles set ticks per second equal to
67 * the frequency. With tickless kernel mode enabled the kernel will not
68 * program a periodic timer at this fast rate.
69 * CONFIG_SYS_CLOCK_TICKS_PER_SEC=32768
70 */
71
72 #define CYCLES_PER_TICK (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC / CONFIG_SYS_CLOCK_TICKS_PER_SEC)
73
74 #define TIMER_BASE (mm_reg_t) DT_INST_REG_ADDR(0)
75 #define TIMER_GIRQ_NUM DT_INST_PROP_BY_IDX(0, girqs, 0)
76 #define TIMER_GIRQ_BITPOS DT_INST_PROP_BY_IDX(0, girqs, 1)
77 /* data sheet GIRQ numbers start at 8 */
78 #define TIMER_GIRQ_BASE \
79 (mm_reg_t)(DT_REG_ADDR(DT_NODELABEL(ecia)) + (GIRQ_SIZE * (TIMER_GIRQ_NUM - 8u)))
80
81 #define TIMER_NVIC_NO DT_INST_IRQN(0)
82 #define TIMER_NVIC_PRIO DT_INST_IRQ(0, priority)
83
84 /* Mask off bits[31:28] of 32-bit count */
85 #define TIMER_MAX 0x0fffffffu
86 #define TIMER_COUNT_MASK 0x0fffffffu
87 #define TIMER_STOPPED 0xf0000000u
88
89 /* Adjust cycle count programmed into timer for HW restart latency */
90 #define TIMER_ADJUST_LIMIT 2
91 #define TIMER_ADJUST_CYCLES 1
92
93 /* max number of ticks we can load into the timer in one shot */
94 #define MAX_TICKS (TIMER_MAX / CYCLES_PER_TICK)
95
96 #ifdef CONFIG_ARCH_HAS_CUSTOM_BUSY_WAIT
97 BUILD_ASSERT(DT_INST_NODE_HAS_PROP(0, busy_wait_timer),
98 "Driver does not not have busy-wait-timer property!");
99
100 #define BTMR_NODE DT_INST_PHANDLE(0, busy_wait_timer)
101
102 BUILD_ASSERT(DT_PROP(BTMR_NODE, max_value) == UINT32_MAX, "Custom busy wait timer is not 32-bit!");
103
104 #define BTMR_BASE (mm_reg_t) DT_REG_ADDR(BTMR_NODE)
105
106 #define BTMR_CNT_OFS 0
107 #define BTMR_PRLD_OFS 4u
108 #define BTMR_SR_OFS 8u
109 #define BTMR_IER_OFS 0xcu
110 #define BTMR_CR_OFS 0x10u
111 #define BTMR_CR_ACTV_POS 0
112 #define BTMR_CR_CNT_UP_POS 2
113 #define BTMR_CR_ARS_POS 3
114 #define BTMR_CR_SOFT_RST_POS 4
115 #define BTMR_CR_START_POS 5
116 #define BTMR_CR_RLD_POS 6
117 #define BTMR_CR_HALT_POS 7
118 #define BTMR_CR_PS_POS 16
119 #define BTMR_CR_PS_MSK GENMASK(31, 16)
120 #define BTMR_CR_PS_SET(n) FIELD_PREP(BTMR_CR_PS_MSK, (n))
121 #define BMTR_CR_PS_GET(n) FIELD_GET(BTMR_CR_PS_MSK, (n))
122
123 #endif
124
125 /*
126 * The spinlock protects all access to the RTMR registers, as well as
127 * 'total_cycles', 'last_announcement', and 'cached_icr'.
128 *
129 * One important invariant that must be observed: `total_cycles` + `cached_icr`
130 * is always an integral multiple of CYCLE_PER_TICK; this is, timer interrupts
131 * are only ever scheduled to occur at tick boundaries.
132 */
133
134 static struct k_spinlock lock;
135 static uint32_t total_cycles;
136 static uint32_t cached_icr = CYCLES_PER_TICK;
137
timer_restart(uint32_t countdown)138 static inline void timer_restart(uint32_t countdown)
139 {
140 sys_write32(0, TIMER_BASE + TIMER_CR_OFS);
141 sys_write32(BIT(TIMER_CR_ACTV_POS), TIMER_BASE + TIMER_CR_OFS);
142 sys_write32(countdown, TIMER_BASE + TIMER_PRLD_OFS);
143 sys_write32(TIMER_START_VAL, TIMER_BASE + TIMER_CR_OFS);
144 }
145
146 /*
147 * Read the RTOS timer counter handling the case where the timer
148 * has been reloaded within 1 32KHz clock of reading its count register.
149 * The RTOS timer hardware must synchronize the write to its control register
150 * on the AHB clock domain with the 32KHz clock domain of its internal logic.
151 * This synchronization can take from nearly 0 time up to 1 32KHz clock as it
152 * depends upon which 48MHz AHB clock with a 32KHz period the register write
153 * was on. We detect the timer is in the load state by checking the read-only
154 * count register and the START bit in the control register. If count register
155 * is 0 and the START bit is set then the timer has been started and is in the
156 * process of moving the preload register value into the count register.
157 */
timer_count(void)158 static inline uint32_t timer_count(void)
159 {
160 uint32_t ccr = sys_read32(TIMER_BASE + TIMER_CNT_OFS);
161
162 if ((ccr == 0) && sys_test_bit(TIMER_BASE + TIMER_CR_OFS, TIMER_CR_START_POS)) {
163 ccr = cached_icr;
164 }
165
166 return ccr;
167 }
168
169 #ifdef CONFIG_TICKLESS_KERNEL
170
171 static uint32_t last_announcement; /* last time we called sys_clock_announce() */
172
173 /*
174 * Request a timeout n Zephyr ticks in the future from now.
175 * Requested number of ticks in the future of n <= 1 means the kernel wants
176 * the tick announced as soon as possible, ideally no more than one tick
177 * in the future.
178 *
179 * Per comment below we don't clear RTMR pending interrupt.
180 * RTMR counter register is read-only and is loaded from the preload
181 * register by a 0->1 transition of the control register start bit.
182 * Writing a new value to preload only takes effect once the count
183 * register reaches 0.
184 */
sys_clock_set_timeout(int32_t n,bool idle)185 void sys_clock_set_timeout(int32_t n, bool idle)
186 {
187 ARG_UNUSED(idle);
188
189 uint32_t ccr, temp;
190 int full_ticks; /* number of complete ticks we'll wait */
191 uint32_t full_cycles; /* full_ticks represented as cycles */
192 uint32_t partial_cycles; /* number of cycles to first tick boundary */
193
194 if (idle && (n == K_TICKS_FOREVER)) {
195 /*
196 * We are not in a locked section. Are writes to two
197 * global objects safe from pre-emption?
198 */
199 sys_write32(0, TIMER_BASE + TIMER_CR_OFS); /* stop timer */
200 cached_icr = TIMER_STOPPED;
201 return;
202 }
203
204 if (n < 1) {
205 full_ticks = 0;
206 } else if ((n == K_TICKS_FOREVER) || (n > MAX_TICKS)) {
207 full_ticks = MAX_TICKS - 1;
208 } else {
209 full_ticks = n - 1;
210 }
211
212 full_cycles = full_ticks * CYCLES_PER_TICK;
213
214 k_spinlock_key_t key = k_spin_lock(&lock);
215
216 ccr = timer_count();
217
218 /* turn off to clear any pending interrupt status */
219 sys_write32(0, TIMER_BASE + TIMER_CR_OFS);
220 sys_write32(BIT(TIMER_GIRQ_BITPOS), TIMER_GIRQ_BASE + GIRQ_SRC_OFS);
221 NVIC_ClearPendingIRQ(TIMER_NVIC_NO);
222
223 temp = total_cycles;
224 temp += (cached_icr - ccr);
225 temp &= TIMER_COUNT_MASK;
226 total_cycles = temp;
227
228 partial_cycles = CYCLES_PER_TICK - (total_cycles % CYCLES_PER_TICK);
229 cached_icr = full_cycles + partial_cycles;
230 /* adjust for up to one 32KHz cycle startup time */
231 temp = cached_icr;
232 if (temp > TIMER_ADJUST_LIMIT) {
233 temp -= TIMER_ADJUST_CYCLES;
234 }
235
236 timer_restart(temp);
237
238 k_spin_unlock(&lock, key);
239 }
240
241 /*
242 * Return the number of Zephyr ticks elapsed from last call to
243 * sys_clock_announce in the ISR. The caller casts uint32_t to int32_t.
244 * We must make sure bit[31] is 0 in the return value.
245 */
sys_clock_elapsed(void)246 uint32_t sys_clock_elapsed(void)
247 {
248 uint32_t ccr;
249 uint32_t ticks;
250 int32_t elapsed;
251
252 k_spinlock_key_t key = k_spin_lock(&lock);
253
254 ccr = timer_count();
255
256 /* It may not look efficient but the compiler does a good job */
257 elapsed = (int32_t)total_cycles - (int32_t)last_announcement;
258 if (elapsed < 0) {
259 elapsed = -1 * elapsed;
260 }
261 ticks = (uint32_t)elapsed;
262 ticks += cached_icr - ccr;
263 ticks /= CYCLES_PER_TICK;
264 ticks &= TIMER_COUNT_MASK;
265
266 k_spin_unlock(&lock, key);
267
268 return ticks;
269 }
270
xec_rtos_timer_isr(const void * arg)271 static void xec_rtos_timer_isr(const void *arg)
272 {
273 ARG_UNUSED(arg);
274
275 uint32_t cycles;
276 int32_t ticks;
277
278 k_spinlock_key_t key = k_spin_lock(&lock);
279
280 sys_write32(BIT(TIMER_GIRQ_BITPOS), TIMER_GIRQ_BASE + GIRQ_SRC_OFS);
281
282 /* Restart the timer as early as possible to minimize drift... */
283 timer_restart(MAX_TICKS * CYCLES_PER_TICK);
284
285 cycles = cached_icr;
286 cached_icr = MAX_TICKS * CYCLES_PER_TICK;
287
288 total_cycles += cycles;
289 total_cycles &= TIMER_COUNT_MASK;
290
291 /* handle wrap by using (power of 2) - 1 mask */
292 ticks = total_cycles - last_announcement;
293 ticks &= TIMER_COUNT_MASK;
294 ticks /= CYCLES_PER_TICK;
295
296 last_announcement = total_cycles;
297
298 k_spin_unlock(&lock, key);
299 sys_clock_announce(ticks);
300 }
301
302 #else
303
304 /* Non-tickless kernel build. */
305
xec_rtos_timer_isr(const void * arg)306 static void xec_rtos_timer_isr(const void *arg)
307 {
308 ARG_UNUSED(arg);
309
310 k_spinlock_key_t key = k_spin_lock(&lock);
311
312 sys_write32(BIT(TIMER_GIRQ_BITPOS), TIMER_GIRQ_BASE + GIRQ_SRC_OFS);
313
314 /* Restart the timer as early as possible to minimize drift... */
315 timer_restart(cached_icr);
316
317 uint32_t temp = total_cycles + CYCLES_PER_TICK;
318
319 total_cycles = temp & TIMER_COUNT_MASK;
320 k_spin_unlock(&lock, key);
321
322 sys_clock_announce(1);
323 }
324
sys_clock_elapsed(void)325 uint32_t sys_clock_elapsed(void)
326 {
327 return 0U;
328 }
329
330 #endif /* CONFIG_TICKLESS_KERNEL */
331
332 /*
333 * Warning RTOS timer resolution is 30.5 us.
334 * This is called by two code paths:
335 * 1. Kernel call to k_cycle_get_32() -> arch_k_cycle_get_32() -> here.
336 * The kernel is casting return to (int) and using it uncasted in math
337 * expressions with int types. Expression result is stored in an int.
338 * 2. If CONFIG_ARCH_HAS_CUSTOM_BUSY_WAIT is not defined then
339 * z_impl_k_busy_wait calls here. This code path uses the value as uint32_t.
340 *
341 */
sys_clock_cycle_get_32(void)342 uint32_t sys_clock_cycle_get_32(void)
343 {
344 uint32_t ret;
345 uint32_t ccr;
346
347 k_spinlock_key_t key = k_spin_lock(&lock);
348
349 ccr = timer_count();
350 ret = (total_cycles + (cached_icr - ccr)) & TIMER_COUNT_MASK;
351
352 k_spin_unlock(&lock, key);
353
354 return ret;
355 }
356
sys_clock_idle_exit(void)357 void sys_clock_idle_exit(void)
358 {
359 if (cached_icr == TIMER_STOPPED) {
360 cached_icr = CYCLES_PER_TICK;
361 timer_restart(cached_icr);
362 }
363 }
364
sys_clock_disable(void)365 void sys_clock_disable(void)
366 {
367 sys_write32(0, TIMER_BASE + TIMER_CR_OFS);
368 }
369
370 #ifdef CONFIG_ARCH_HAS_CUSTOM_BUSY_WAIT
371
372 /*
373 * We implement custom busy wait using a MEC1501 basic timer running on
374 * the 48MHz clock domain. This code is here for future power management
375 * save/restore of the timer context.
376 */
377
378 /*
379 * 32-bit basic timer 0 configured for 1MHz count up, auto-reload,
380 * and no interrupt generation.
381 */
arch_busy_wait(uint32_t usec_to_wait)382 void arch_busy_wait(uint32_t usec_to_wait)
383 {
384 if (usec_to_wait == 0) {
385 return;
386 }
387
388 uint32_t start = sys_read32(BTMR_BASE + BTMR_CNT_OFS);
389
390 for (;;) {
391 uint32_t curr = sys_read32(BTMR_BASE + BTMR_CNT_OFS);
392
393 if ((curr - start) >= usec_to_wait) {
394 break;
395 }
396 }
397 }
398 #endif
399
sys_clock_driver_init(void)400 static int sys_clock_driver_init(void)
401 {
402 #ifdef CONFIG_TICKLESS_KERNEL
403 cached_icr = MAX_TICKS;
404 #endif
405
406 sys_write32(0, TIMER_BASE + TIMER_CR_OFS);
407 sys_write32(BIT(TIMER_GIRQ_BITPOS), TIMER_GIRQ_BASE + GIRQ_ENCLR_OFS);
408 sys_write32(BIT(TIMER_GIRQ_BITPOS), TIMER_GIRQ_BASE + GIRQ_SRC_OFS);
409 NVIC_ClearPendingIRQ(TIMER_NVIC_NO);
410
411 IRQ_CONNECT(TIMER_NVIC_NO, TIMER_NVIC_PRIO, xec_rtos_timer_isr, 0, 0);
412 irq_enable(TIMER_NVIC_NO);
413 sys_write32(BIT(TIMER_GIRQ_BITPOS), TIMER_GIRQ_BASE + GIRQ_ENSET_OFS);
414
415 #ifdef CONFIG_ARCH_HAS_CUSTOM_BUSY_WAIT
416 uint32_t btmr_ctrl = (BIT(BTMR_CR_ACTV_POS) | BIT(BTMR_CR_ARS_POS) |
417 BIT(BTMR_CR_CNT_UP_POS) | BTMR_CR_PS_SET(47u));
418
419 sys_write32(BIT(BTMR_CR_SOFT_RST_POS), BTMR_BASE + BTMR_CR_OFS);
420 sys_write32(btmr_ctrl, BTMR_BASE + BTMR_CR_OFS);
421 sys_write32(UINT32_MAX, BTMR_BASE + BTMR_PRLD_OFS);
422 sys_set_bit(BTMR_BASE + BTMR_CR_OFS, BTMR_CR_START_POS);
423
424 timer_restart(cached_icr);
425 /* wait for RTOS timer to load count register from preload */
426 while (sys_read32(BTMR_BASE + BTMR_CNT_OFS) == 0) {
427 ;
428 }
429 #else
430 timer_restart(cached_icr);
431 #endif
432
433 return 0;
434 }
435
436 SYS_INIT(sys_clock_driver_init, PRE_KERNEL_2, CONFIG_SYSTEM_CLOCK_INIT_PRIORITY);
437
