1 /*
2  * Copyright (c) 2024 BayLibre, SAS
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 #define DT_DRV_COMPAT ti_cc23x0_rtc_timer
8 
9 #include <soc.h>
10 
11 #include <zephyr/device.h>
12 #include <zephyr/drivers/clock_control.h>
13 #include <zephyr/drivers/timer/system_timer.h>
14 #include <zephyr/irq.h>
15 #include <zephyr/spinlock.h>
16 #include <zephyr/sys_clock.h>
17 #include <zephyr/sys/util.h>
18 
19 #include <inc/hw_rtc.h>
20 #include <inc/hw_types.h>
21 #include <inc/hw_evtsvt.h>
22 #include <inc/hw_memmap.h>
23 
24 #define RTC_TIMEOUT_MAX 0xFFBFFFFFU
25 
26 /* Set rtc interrupt to lowest priority */
27 #define SYSTIM_ISR_PRIORITY 3U
28 
29 /* Keep track of rtc counter at previous announcement to the kernel */
30 static uint32_t last_rtc_count;
31 
32 #define TICK_PERIOD_MICRO_SEC (1000000 / CONFIG_SYS_CLOCK_TICKS_PER_SEC)
33 
sys_clock_set_timeout(int32_t ticks,bool idle)34 void sys_clock_set_timeout(int32_t ticks, bool idle)
35 {
36 	ARG_UNUSED(idle);
37 
38 	/* If timeout is necessary */
39 	if (ticks != K_TICKS_FOREVER) {
40 		/* Get current value as early as possible */
41 		uint32_t ticks_now = HWREG(RTC_BASE + RTC_O_TIME8U);
42 
43 		if ((ticks_now + ticks) >= RTC_TIMEOUT_MAX) {
44 			/* Reset timer and start from 0 */
45 			HWREG(RTC_BASE + RTC_O_CTL) = RTC_CTL_RST_CLR;
46 			HWREG(RTC_BASE + RTC_O_CH0CC8U) = ticks;
47 		}
48 
49 		HWREG(RTC_BASE + RTC_O_CH0CC8U) = ticks_now + ticks;
50 	}
51 }
52 
get_elapsed_ticks_rtc(uint32_t current_rtc_count)53 uint32_t get_elapsed_ticks_rtc(uint32_t current_rtc_count)
54 {
55 	if (current_rtc_count >= last_rtc_count) {
56 		return (current_rtc_count - last_rtc_count);
57 	} else {
58 		return ((0xFFFFFFFF - last_rtc_count) + current_rtc_count);
59 	}
60 }
61 
sys_clock_elapsed(void)62 uint32_t sys_clock_elapsed(void)
63 {
64 	int32_t elapsed_ticks = get_elapsed_ticks_rtc(HWREG(RTC_BASE + RTC_O_TIME8U)) /
65 						      TICK_PERIOD_MICRO_SEC;
66 
67 	return elapsed_ticks;
68 }
69 
sys_clock_cycle_get_32(void)70 uint32_t sys_clock_cycle_get_32(void)
71 {
72 	return HWREG(RTC_BASE + RTC_O_TIME8U);
73 }
74 
rtc_isr(const void * arg)75 static void rtc_isr(const void *arg)
76 {
77 	uint32_t current_rtc_count = HWREG(RTC_BASE + RTC_O_TIME8U);
78 	int32_t elapsed_ticks = get_elapsed_ticks_rtc(current_rtc_count);
79 
80 	HWREG(RTC_BASE + RTC_O_ICLR) = RTC_ICLR_EV0_CLR;
81 
82 	sys_clock_announce(elapsed_ticks);
83 
84 	last_rtc_count = current_rtc_count;
85 }
86 
sys_clock_driver_init(void)87 static int sys_clock_driver_init(void)
88 {
89 	uint32_t now_ticks;
90 
91 	now_ticks = HWREG(RTC_BASE + RTC_O_TIME8U);
92 	last_rtc_count = now_ticks;
93 
94 	HWREG(RTC_BASE + RTC_O_ICLR) = RTC_ICLR_EV0_CLR | RTC_ICLR_EV1_CLR;
95 	HWREG(RTC_BASE + RTC_O_IMCLR) = RTC_IMCLR_EV0_CLR | RTC_IMCLR_EV1_CLR;
96 
97 	HWREG(EVTSVT_BASE + EVTSVT_O_CPUIRQ16SEL) = EVTSVT_CPUIRQ16SEL_PUBID_AON_RTC_COMB;
98 	HWREG(RTC_BASE + RTC_O_CH0CC8U) = now_ticks + RTC_TIMEOUT_MAX;
99 
100 	HWREG(RTC_BASE + RTC_O_IMASK) = RTC_IMASK_EV0_EN;
101 	HWREG(RTC_BASE + RTC_O_ARMSET) = RTC_ARMSET_CH0_SET;
102 
103 	/* Take configurable interrupt IRQ16 for rtc */
104 	IRQ_CONNECT(CPUIRQ16_IRQn, SYSTIM_ISR_PRIORITY, rtc_isr, 0, 0);
105 	irq_enable(CPUIRQ16_IRQn);
106 
107 	return 0;
108 }
109 
110 SYS_INIT(sys_clock_driver_init, PRE_KERNEL_2, CONFIG_SYSTEM_CLOCK_INIT_PRIORITY);
111