1 /*
2 * Copyright (c) 2025 Andrew Featherstone
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT hazard3_hazard3_intc
8
9 #include <zephyr/kernel.h>
10 #include <zephyr/arch/cpu.h>
11 #include <zephyr/irq.h>
12 #include <zephyr/device.h>
13 #include <zephyr/types.h>
14 #include <zephyr/arch/riscv/csr.h>
15 #include <zephyr/arch/riscv/irq.h>
16
17 #include <pico/runtime_init.h>
18 #include <hardware/irq.h>
19
20 #define CSR_WINDOW_SIZE 16
21
arch_irq_enable(unsigned int irq)22 void arch_irq_enable(unsigned int irq)
23 {
24 irq_set_enabled(irq, true);
25 }
26
arch_irq_disable(unsigned int irq)27 void arch_irq_disable(unsigned int irq)
28 {
29 irq_set_enabled(irq, false);
30 }
31
arch_irq_is_enabled(unsigned int irq)32 int arch_irq_is_enabled(unsigned int irq)
33 {
34 return pico_irq_is_enabled(irq);
35 }
36
hazard3_irq_init(const struct device * dev)37 static int hazard3_irq_init(const struct device *dev)
38 {
39 /* Clear all IRQ force array bits. */
40 for (int i = 0; (i * CSR_WINDOW_SIZE) < CONFIG_NUM_IRQS; i++) {
41 hazard3_irqarray_clear(RVCSR_MEIFA_OFFSET, i, -1);
42 }
43
44 /* Global external IRQ enable. */
45 csr_write(mie, RVCSR_MIE_MEIE_BITS);
46
47 csr_set(mstatus, MSTATUS_IEN);
48
49 return 0;
50 }
51
52 DEVICE_DT_INST_DEFINE(0, hazard3_irq_init, NULL, NULL, NULL,
53 PRE_KERNEL_1, CONFIG_INTC_INIT_PRIORITY, NULL);
54
