1# Common architecture configuration options
2
3# Copyright (c) 2022, CSIRO.
4# Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
5# SPDX-License-Identifier: Apache-2.0
6
7config SEMIHOST
8	bool "Semihosting support for ARM, RISC-V and Xtensa targets"
9	depends on ARM || ARM64 || RISCV || (XTENSA && !SIMULATOR_XTENSA)
10	help
11	  Semihosting is a mechanism that enables code running on an ARM, RISC-V
12	  or Xtensa target to communicate and use the Input/Output facilities on
13	  a host computer that is running a debugger.
14	  Additional information can be found in:
15	  https://developer.arm.com/documentation/dui0471/m/what-is-semihosting-
16	  https://github.com/riscv-non-isa/riscv-semihosting/blob/main/riscv-semihosting.adoc
17	  This option is compatible with hardware and with QEMU, through the
18	  (automatic) use of the -semihosting-config switch when invoking it.
19
20config ISR_TABLE_SHELL
21	bool "Shell command to dump the ISR tables"
22	depends on GEN_SW_ISR_TABLE
23	depends on SHELL
24	help
25	  This option enables a shell command to dump the ISR tables.
26
27config ARCH_SUPPORTS_ROM_OFFSET
28	bool
29	default y
30	depends on  (ARM || X86 || ARM64 || RISCV || ARC)
31	help
32	  Hidden option to enable support for ROM offset within the linker
33	  script, which will place a block of 0x0 of size
34	  CONFIG_ROM_START_OFFSET at the start of the ROM region.
35
36config ARM_MPU
37	bool "ARM MPU Support"
38	select MPU
39	select SRAM_REGION_PERMISSIONS
40	select THREAD_STACK_INFO
41	select ARCH_HAS_EXECUTABLE_PAGE_BIT if (CPU_AARCH32_CORTEX_R || CPU_CORTEX_M)
42	select MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT if !(CPU_HAS_NXP_SYSMPU || ARMV8_M_BASELINE || ARMV8_M_MAINLINE || AARCH32_ARMV8_R)
43	select MPU_REQUIRES_NON_OVERLAPPING_REGIONS if CPU_HAS_ARM_MPU && (ARMV8_M_BASELINE || ARMV8_M_MAINLINE || AARCH32_ARMV8_R)
44	select MPU_GAP_FILLING if AARCH32_ARMV8_R
45	select ARCH_MEM_DOMAIN_SUPPORTS_ISOLATED_STACKS if (CPU_AARCH32_CORTEX_R || CPU_CORTEX_M)
46	select ARCH_MEM_DOMAIN_SYNCHRONOUS_API if USERSPACE && CPU_AARCH64_CORTEX_R
47	default y if CPU_AARCH64_CORTEX_R
48	depends on CPU_HAS_MPU
49	help
50	  MCU implements Memory Protection Unit.
51
52	  Notes:
53	  The ARMv6-M, ARMv7-M, and ARMv8-R MPU MPU architecture requires a power-of-two
54	  alignment of MPU region base address and size.
55
56	  The NXP MPU as well as the ARMv8-M MPU do not require MPU regions
57	  to have power-of-two alignment for base address and region size.
58
59	  The ARMv8-M and ARMv8-R MPU requires the active MPU regions be non-overlapping.
60	  As a result of this, both respective MPUs needs to fully partition the
61	  memory map when programming dynamic memory regions (e.g. PRIV stack
62	  guard, user thread stack, and application memory domains), if the
63	  system requires PRIV access policy different from the access policy
64	  of the ARMv8-M or ARMv8-R background memory map. The application developer may
65	  enforce full PRIV (kernel) memory partition by enabling the
66	  MPU_GAP_FILLING option.
67	  By not enforcing full partition, MPU may leave part of kernel
68	  SRAM area covered only by the default ARMv8-M or ARMv8-R memory map. This
69	  is fine for User Mode, since the background ARM map does not
70	  allow nPRIV access at all. However, since the background map
71	  policy allows instruction fetches by privileged code, forcing
72	  this Kconfig option off prevents the system from directly
73	  triggering MemManage exceptions upon accidental attempts to
74	  execute code from SRAM in XIP builds.
75	  Since this does not compromise User Mode, we make the skipping
76	  of full partitioning the default behavior for the ARMv8-M and ARMv8-R MPU
77	  driver.
78
79config ARM_PAC_PER_THREAD
80	bool "Set cryptographically secure PAC key per thread"
81	depends on ARM_PAC
82	depends on ENTROPY_DEVICE_RANDOM_GENERATOR || TIMER_RANDOM_GENERATOR
83	help
84	  Select this option to generate and use unique keys per thread to generate Pointer
85	  Authentication Code.
86	  Internally, sys_csrand_get() is used as part of arch_new_thread() to generate
87	  cryptographically secure random keys, which are saved in the thread's
88	  architecture-specific context. These keys are then loaded into the PAC key registers
89	  before switching to the thread during context switches.
90	  Applications can chose to have hardware based random keys generator by selecting the right
91	  generator from RNG_GENERATOR_CHOICE or by selecting TIMER_RANDOM_GENERATOR for testing
92	  with pseudo random keys.
93	  Note: GCC version 14.3 or higher is needed to support this option.
94
95config ARM_PAC
96	bool
97	help
98	  This option signifies that Pointer Authentication Code is enabled.
99
100config ARM_BTI
101	bool
102	help
103	  This option signifies that Branch Target Identification is enabled.
104
105choice ARM_PACBTI
106	prompt "Pointer Authentication and Branch Target Identification (PACBTI)"
107	default ARM_PACBTI_NONE
108	depends on ARMV8_1_M_MAINLINE
109	help
110	  Select a PACBTI configuration to enable the compiler to insert the required
111	  Pointer Authentication and Branch Target Identification (PACBTI) instructions.
112	  This also sets the necessary configuration options to enable PACBTI bits
113	  in hardware.
114
115config ARM_PACBTI_STANDARD
116	bool "Standard (PACRET + LEAF + BTI)"
117	select ARM_PAC
118	select ARM_BTI
119	help
120	  This option instructs the compiler to generate code with all branch protection features
121	  enabled at their standard level.
122
123config ARM_PACBTI_PACRET
124	bool "PACRET only"
125	select ARM_PAC
126	help
127	  This option instructs the compiler to generate code with return address signing for
128	  all functions that save the return address to memory.
129
130config ARM_PACBTI_PACRET_LEAF
131	bool "PACRET + Leaf"
132	select ARM_PAC
133	help
134	  This option instructs the compiler to generate code with return address signing for
135	  all functions that save the return address to memory and,
136	  also sign leaf functions even if they do not write the return address to memory.
137
138config ARM_PACBTI_BTI
139	bool "BTI only"
140	select ARM_BTI
141	help
142	  This option enables Branch Target Identification (BTI), which inserts special landing
143	  pad instructions at valid indirect branch targets. This option does not enable Pointer
144	  Authentication (PAC).
145
146config ARM_PACBTI_PACRET_BTI
147	bool "PACRET + BTI"
148	select ARM_PAC
149	select ARM_BTI
150	help
151	  This option instructs the compiler to generate code with return address signing for
152	  all functions that save the return address to memory and,
153	  add landing-pad instructions at the permitted targets of indirect branch instructions
154
155config ARM_PACBTI_PACRET_LEAF_BTI
156	bool "PACRET + Leaf + BTI"
157	select ARM_PAC
158	select ARM_BTI
159	help
160	  This option instructs the compiler to generate code with return address signing for
161	  all functions that save the return address to memory and,
162	  also sign leaf functions even if they do not write the return address to memory and,
163	  add landing-pad instructions at the permitted targets of indirect branch instructions
164
165config ARM_PACBTI_NONE
166	bool "None"
167	help
168	This option instructs the compiler to generate code without branch protection or return
169	address signing
170endchoice
171