1 /*
2 * Copyright (c) 2016 Intel Corporation
3 * Copyright 2024 NXP
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8 #include <zephyr/pm/device_runtime.h>
9 #include "test_gpio.h"
10
11 /* Grotesque hack for pinmux boards */
12 #if defined(CONFIG_BOARD_RV32M1_VEGA)
13 #include <fsl_port.h>
14 #elif defined(CONFIG_BOARD_UDOO_NEO_FULL_MCIMX6X_M4)
15 #include "device_imx.h"
16 #elif defined(CONFIG_BOARD_MIMXRT1050_EVK)
17 #include <fsl_iomuxc.h>
18 #elif defined(CONFIG_BOARD_NRF52_BSIM)
19 #include <NRF_GPIO.h>
20 #endif
21
board_setup(void)22 static void board_setup(void)
23 {
24 #if defined(CONFIG_BOARD_UDOO_NEO_FULL_MCIMX6X_M4)
25 /*
26 * Configure pin mux.
27 * The following code needs to configure the same GPIOs which were
28 * selected as test pins in device tree.
29 */
30
31 if (PIN_IN != 15) {
32 printk("FATAL: input pin set in DTS %d != %d\n", PIN_IN, 15);
33 k_panic();
34 }
35
36 if (PIN_OUT != 14) {
37 printk("FATAL: output pin set in DTS %d != %d\n", PIN_OUT, 14);
38 k_panic();
39 }
40
41 /* Configure pin RGMII2_RD2 as GPIO5_IO14. */
42 IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD2 =
43 IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD2_MUX_MODE(5);
44 /* Select pull enabled, speed 100 MHz, drive strength 43 ohm */
45 IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD2 =
46 IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD2_PUE_MASK |
47 IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD2_PKE_MASK |
48 IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD2_SPEED(2) |
49 IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD2_DSE(6);
50
51 /* Configure pin RGMII2_RD3 as GPIO5_IO15. */
52 IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD3 =
53 IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD3_MUX_MODE(5);
54 /* Select pull enabled, speed 100 MHz, drive strength 43 ohm */
55 IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD3 =
56 IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD3_PUE_MASK |
57 IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD3_PKE_MASK |
58 IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD3_SPEED(2) |
59 IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD3_DSE(6);
60 #elif defined(CONFIG_GPIO_EMUL)
61 extern struct gpio_callback gpio_emul_callback;
62 const struct device *const dev = DEVICE_DT_GET(DEV);
63
64 zassert_true(device_is_ready(dev), "GPIO dev is not ready");
65 int rc = gpio_add_callback(dev, &gpio_emul_callback);
66 __ASSERT(rc == 0, "gpio_add_callback() failed: %d", rc);
67 #elif defined(CONFIG_BOARD_NRF52_BSIM)
68 static bool done;
69
70 if (!done) {
71 done = true;
72 /* This functions allows to programmatically short-circuit SOC GPIO pins */
73 nrf_gpio_backend_register_short(1, PIN_OUT, 1, PIN_IN);
74 }
75 #endif
76 }
77
gpio_basic_setup(void)78 static void *gpio_basic_setup(void)
79 {
80 board_setup();
81 (void)pm_device_runtime_get(DEVICE_DT_GET(DEV));
82 #ifdef CONFIG_UART_CONSOLE
83 (void)pm_device_runtime_get(DEVICE_DT_GET(DT_CHOSEN(zephyr_console)));
84 #endif
85 return NULL;
86 }
87
gpio_basic_teardown(void * args)88 void gpio_basic_teardown(void *args)
89 {
90 (void)args;
91 (void)pm_device_runtime_put(DEVICE_DT_GET(DEV));
92 #ifdef CONFIG_UART_CONSOLE
93 (void)pm_device_runtime_put(DEVICE_DT_GET(DT_CHOSEN(zephyr_console)));
94 #endif
95 }
96
97 /* Test GPIO port configuration */
98 ZTEST_SUITE(gpio_port, NULL, gpio_basic_setup, NULL, NULL, gpio_basic_teardown);
99
100 /* Test GPIO callback management */
101 ZTEST_SUITE(gpio_port_cb_mgmt, NULL, gpio_basic_setup, NULL, NULL, gpio_basic_teardown);
102
103 /* Test GPIO callbacks */
104 ZTEST_SUITE(gpio_port_cb_vari, NULL, gpio_basic_setup, NULL, NULL, gpio_basic_teardown);
105
106 /* Test GPIO port configuration influence on callbacks. Want to run just
107 * after flash, hence the name starting in 'a'
108 */
109 ZTEST_SUITE(after_flash_gpio_config_trigger, NULL, gpio_basic_setup, NULL, NULL,
110 gpio_basic_teardown);
111
