1 /*
2 * Copyright 2023 NXP
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 /*
8 * Based on DMIC driver sample, which is:
9 * Copyright (c) 2021 Nordic Semiconductor ASA
10 */
11
12 #include <zephyr/kernel.h>
13 #include <zephyr/audio/dmic.h>
14 #include <zephyr/ztest.h>
15
16 static const struct device *dmic_dev = DEVICE_DT_GET(DT_ALIAS(dmic_dev));
17
18 #define SAMPLE_BIT_WIDTH CONFIG_SAMPLE_BIT_WIDTH
19 #define PDM_CHANNELS CONFIG_SAMPLE_PDM_CHANNELS
20 #define BYTES_PER_SAMPLE SAMPLE_BIT_WIDTH / 8
21 #define SLAB_ALIGN 4
22 #define MAX_SAMPLE_RATE 48000
23
24 /* Milliseconds to wait for a block to be read. */
25 #define READ_TIMEOUT 1000
26 /* Size of a block for 100 ms of audio data. */
27 #if defined(CONFIG_COVERAGE)
28 /* Use smaller buffer in coverage mode. */
29 #define BLOCK_SIZE(_sample_rate, _number_of_channels) \
30 (BYTES_PER_SAMPLE * (_sample_rate / 100) * _number_of_channels)
31 #else
32 #define BLOCK_SIZE(_sample_rate, _number_of_channels) \
33 (BYTES_PER_SAMPLE * (_sample_rate / 10) * _number_of_channels)
34 #endif
35
36 /* Driver will allocate blocks from this slab to receive audio data into them.
37 * Application, after getting a given block from the driver and processing its
38 * data, needs to free that block.
39 */
40 #define MAX_BLOCK_SIZE BLOCK_SIZE(MAX_SAMPLE_RATE, PDM_CHANNELS)
41 #define BLOCK_COUNT 8
42 K_MEM_SLAB_DEFINE_STATIC(mem_slab, MAX_BLOCK_SIZE, BLOCK_COUNT, SLAB_ALIGN);
43
44 static struct pcm_stream_cfg pcm_stream = {
45 .pcm_width = SAMPLE_BIT_WIDTH,
46 .mem_slab = &mem_slab,
47 };
48 static struct dmic_cfg dmic_cfg = {
49 .io = {
50 /* These fields can be used to limit the PDM clock
51 * configurations that the driver is allowed to use
52 * to those supported by the microphone.
53 */
54 .min_pdm_clk_freq = 1000000,
55 .max_pdm_clk_freq = 3500000,
56 .min_pdm_clk_dc = 40,
57 .max_pdm_clk_dc = 60,
58 },
59 .streams = &pcm_stream,
60 .channel = {
61 .req_num_streams = 1,
62 },
63 };
64
65 /* Verify that dmic_trigger fails when DMIC is not configured
66 * this test must run first, before DMIC has been configured
67 */
ZTEST(dmic,test_0_start_fail)68 ZTEST(dmic, test_0_start_fail)
69 {
70 int ret;
71
72 zassert_true(device_is_ready(dmic_dev), "DMIC device is not ready");
73 ret = dmic_trigger(dmic_dev, DMIC_TRIGGER_START);
74 zassert_not_equal(ret, 0, "DMIC trigger should fail when DMIC is not configured");
75 }
76
do_pdm_transfer(const struct device * dmic,struct dmic_cfg * cfg)77 static int do_pdm_transfer(const struct device *dmic,
78 struct dmic_cfg *cfg)
79 {
80 int ret;
81 void *buffer;
82 uint32_t size;
83
84 TC_PRINT("PCM output rate: %u, channels: %u\n",
85 cfg->streams[0].pcm_rate, cfg->channel.req_num_chan);
86
87 ret = dmic_configure(dmic, cfg);
88 if (ret < 0) {
89 TC_PRINT("DMIC configuration failed: %d\n", ret);
90 return ret;
91 }
92
93 /* Check that the driver is properly populating the "act*" fields */
94 zassert_equal(cfg->channel.act_num_chan,
95 cfg->channel.req_num_chan,
96 "DMIC configure should populate act_num_chan field");
97 zassert_equal(cfg->channel.act_chan_map_lo,
98 cfg->channel.req_chan_map_lo,
99 "DMIC configure should populate act_chan_map_lo field");
100 zassert_equal(cfg->channel.act_chan_map_hi,
101 cfg->channel.req_chan_map_hi,
102 "DMIC configure should populate act_chan_map_hi field");
103 ret = dmic_trigger(dmic, DMIC_TRIGGER_START);
104 if (ret < 0) {
105 TC_PRINT("DMIC start trigger failed: %d\n", ret);
106 return ret;
107 }
108
109 /* We read more than the total BLOCK_COUNT to insure the DMIC
110 * driver correctly reallocates memory slabs as it exhausts existing
111 * ones.
112 */
113 for (int i = 0; i < (2 * BLOCK_COUNT); i++) {
114 ret = dmic_read(dmic, 0, &buffer, &size, READ_TIMEOUT);
115 if (ret < 0) {
116 TC_PRINT("DMIC read failed: %d\n", ret);
117 return ret;
118 }
119
120 TC_PRINT("%d - got buffer %p of %u bytes\n", i, buffer, size);
121 k_mem_slab_free(&mem_slab, buffer);
122 }
123
124 ret = dmic_trigger(dmic, DMIC_TRIGGER_STOP);
125 if (ret < 0) {
126 TC_PRINT("DMIC stop trigger failed: %d\n", ret);
127 return ret;
128 }
129 return 0;
130 }
131
132
133 /* Verify that the DMIC can transfer from a single channel */
ZTEST(dmic,test_single_channel)134 ZTEST(dmic, test_single_channel)
135 {
136 dmic_cfg.channel.req_num_chan = 1;
137 dmic_cfg.channel.req_chan_map_lo =
138 dmic_build_channel_map(0, 0, PDM_CHAN_LEFT);
139 dmic_cfg.streams[0].pcm_rate = MAX_SAMPLE_RATE;
140 dmic_cfg.streams[0].block_size =
141 BLOCK_SIZE(dmic_cfg.streams[0].pcm_rate,
142 dmic_cfg.channel.req_num_chan);
143 zassert_equal(do_pdm_transfer(dmic_dev, &dmic_cfg), 0,
144 "Single channel transfer failed");
145 }
146
147 /* Verify that the DMIC can transfer from a L/R channel pair */
ZTEST(dmic,test_stereo_channel)148 ZTEST(dmic, test_stereo_channel)
149 {
150 dmic_cfg.channel.req_num_chan = 2;
151 dmic_cfg.channel.req_chan_map_lo =
152 dmic_build_channel_map(0, 0, PDM_CHAN_LEFT) |
153 dmic_build_channel_map(1, 0, PDM_CHAN_RIGHT);
154 dmic_cfg.streams[0].pcm_rate = MAX_SAMPLE_RATE;
155 dmic_cfg.streams[0].block_size =
156 BLOCK_SIZE(dmic_cfg.streams[0].pcm_rate,
157 dmic_cfg.channel.req_num_chan);
158 zassert_equal(do_pdm_transfer(dmic_dev, &dmic_cfg), 0,
159 "L/R channel transfer failed");
160 dmic_cfg.channel.req_chan_map_lo =
161 dmic_build_channel_map(0, 0, PDM_CHAN_RIGHT) |
162 dmic_build_channel_map(1, 0, PDM_CHAN_LEFT);
163 zassert_equal(do_pdm_transfer(dmic_dev, &dmic_cfg), 0,
164 "R/L channel transfer failed");
165 }
166
167 /* Test DMIC with maximum number of channels */
ZTEST(dmic,test_max_channel)168 ZTEST(dmic, test_max_channel)
169 {
170 enum pdm_lr lr;
171 uint8_t pdm_hw_chan;
172
173 dmic_cfg.channel.req_num_chan = PDM_CHANNELS;
174 dmic_cfg.channel.req_chan_map_lo = 0;
175 dmic_cfg.channel.req_chan_map_hi = 0;
176 for (uint8_t i = 0; i < PDM_CHANNELS; i++) {
177 lr = ((i % 2) == 0) ? PDM_CHAN_LEFT : PDM_CHAN_RIGHT;
178 pdm_hw_chan = i >> 1;
179 if (i < 4) {
180 dmic_cfg.channel.req_chan_map_lo |=
181 dmic_build_channel_map(i, pdm_hw_chan, lr);
182 } else {
183 dmic_cfg.channel.req_chan_map_hi |=
184 dmic_build_channel_map(i, pdm_hw_chan, lr);
185 }
186 }
187
188 dmic_cfg.streams[0].pcm_rate = MAX_SAMPLE_RATE;
189 dmic_cfg.streams[0].block_size =
190 BLOCK_SIZE(dmic_cfg.streams[0].pcm_rate,
191 dmic_cfg.channel.req_num_chan);
192 zassert_equal(do_pdm_transfer(dmic_dev, &dmic_cfg), 0,
193 "Maximum channel transfer failed");
194 }
195
196 /* Test pausing and restarting a channel */
ZTEST(dmic,test_pause_restart)197 ZTEST(dmic, test_pause_restart)
198 {
199 int ret, i;
200 void *buffer;
201 uint32_t size;
202
203 dmic_cfg.channel.req_num_chan = 1;
204 dmic_cfg.channel.req_chan_map_lo =
205 dmic_build_channel_map(0, 0, PDM_CHAN_LEFT);
206 dmic_cfg.streams[0].pcm_rate = MAX_SAMPLE_RATE;
207 dmic_cfg.streams[0].block_size =
208 BLOCK_SIZE(dmic_cfg.streams[0].pcm_rate,
209 dmic_cfg.channel.req_num_chan);
210 ret = dmic_configure(dmic_dev, &dmic_cfg);
211 zassert_equal(ret, 0, "DMIC configure failed");
212
213 /* Start the DMIC, and pause it immediately */
214 ret = dmic_trigger(dmic_dev, DMIC_TRIGGER_START);
215 zassert_equal(ret, 0, "DMIC start failed");
216 ret = dmic_trigger(dmic_dev, DMIC_TRIGGER_PAUSE);
217 zassert_equal(ret, 0, "DMIC pause failed");
218 /* There may be some buffers in the DMIC queue, but a read
219 * should eventually time out while it is paused
220 */
221 for (i = 0; i < (2 * BLOCK_COUNT); i++) {
222 ret = dmic_read(dmic_dev, 0, &buffer, &size, READ_TIMEOUT);
223 if (ret < 0) {
224 break;
225 }
226 k_mem_slab_free(&mem_slab, buffer);
227 }
228 zassert_not_equal(ret, 0, "DMIC is paused, reads should timeout");
229 TC_PRINT("Queue drained after %d reads\n", i);
230 /* Unpause the DMIC */
231 ret = dmic_trigger(dmic_dev, DMIC_TRIGGER_RELEASE);
232 zassert_equal(ret, 0, "DMIC release failed");
233 /* Reads should not timeout now */
234 for (i = 0; i < (2 * BLOCK_COUNT); i++) {
235 ret = dmic_read(dmic_dev, 0, &buffer, &size, READ_TIMEOUT);
236 if (ret < 0) {
237 break;
238 }
239 k_mem_slab_free(&mem_slab, buffer);
240 }
241 zassert_equal(ret, 0, "DMIC is active, reads should succeed");
242 TC_PRINT("%d reads completed\n", (2 * BLOCK_COUNT));
243 /* Stop the DMIC, and repeat the same tests */
244 ret = dmic_trigger(dmic_dev, DMIC_TRIGGER_STOP);
245 zassert_equal(ret, 0, "DMIC stop failed");
246 /* Versus a pause, DMIC reads should immediately stop once DMIC times
247 * out
248 */
249 ret = dmic_read(dmic_dev, 0, &buffer, &size, READ_TIMEOUT);
250 zassert_not_equal(ret, 0, "DMIC read should timeout when DMIC is stopped");
251 ret = dmic_trigger(dmic_dev, DMIC_TRIGGER_START);
252 zassert_equal(ret, 0, "DMIC restart failed");
253 /* Reads should not timeout now */
254 for (i = 0; i < (2 * BLOCK_COUNT); i++) {
255 ret = dmic_read(dmic_dev, 0, &buffer, &size, READ_TIMEOUT);
256 if (ret < 0) {
257 break;
258 }
259 k_mem_slab_free(&mem_slab, buffer);
260 }
261 zassert_equal(ret, 0, "DMIC is active, reads should succeed");
262 TC_PRINT("%d reads completed\n", (2 * BLOCK_COUNT));
263 /* Test is over. Stop the DMIC */
264 ret = dmic_trigger(dmic_dev, DMIC_TRIGGER_STOP);
265 zassert_equal(ret, 0, "DMIC stop failed");
266 }
267
268 /* Verify that channel map without adjacent L/R pairs fails */
ZTEST(dmic,test_bad_pair)269 ZTEST(dmic, test_bad_pair)
270 {
271 int ret;
272
273 dmic_cfg.channel.req_num_chan = 2;
274 dmic_cfg.channel.req_chan_map_lo =
275 dmic_build_channel_map(0, 0, PDM_CHAN_RIGHT) |
276 dmic_build_channel_map(1, 0, PDM_CHAN_RIGHT);
277 dmic_cfg.streams[0].pcm_rate = MAX_SAMPLE_RATE;
278 dmic_cfg.streams[0].block_size =
279 BLOCK_SIZE(dmic_cfg.streams[0].pcm_rate,
280 dmic_cfg.channel.req_num_chan);
281 ret = dmic_configure(dmic_dev, &dmic_cfg);
282 zassert_not_equal(ret, 0, "DMIC configure should fail with "
283 "two of same channel in map");
284
285 dmic_cfg.channel.req_num_chan = 2;
286 dmic_cfg.channel.req_chan_map_lo =
287 dmic_build_channel_map(0, 0, PDM_CHAN_RIGHT) |
288 dmic_build_channel_map(1, 1, PDM_CHAN_LEFT);
289 ret = dmic_configure(dmic_dev, &dmic_cfg);
290 zassert_not_equal(ret, 0, "DMIC configure should fail with "
291 "non adjacent channels in map");
292 }
293
294 ZTEST_SUITE(dmic, NULL, NULL, NULL, NULL, NULL);
295
